Commit 6ba3f59e authored by Peng Ju Zhou's avatar Peng Ju Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c 



In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.

Signed-off-by: default avatarPeng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f2958a8b

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+7 −2
Original line number Diff line number Diff line
@@ -629,13 +629,18 @@ void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 
	for (i = 0; i < 16; i++) {

		reg = hub->vm_context0_cntl + hub->ctx_distance * i;



		tmp = RREG32(reg);

		tmp = (hub_type == AMDGPU_GFXHUB_0) ?

			RREG32_SOC15_IP(GC, reg) :

			RREG32_SOC15_IP(MMHUB, reg);



		if (enable)

			tmp |= hub->vm_cntx_cntl_vm_fault;

		else

			tmp &= ~hub->vm_cntx_cntl_vm_fault;



		WREG32(reg, tmp);

		(hub_type == AMDGPU_GFXHUB_0) ?

			WREG32_SOC15_IP(GC, reg, tmp) :

			WREG32_SOC15_IP(MMHUB, reg, tmp);

	}

}

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+17 −8
Original line number Diff line number Diff line
@@ -229,6 +229,10 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 
	/* Use register 17 for GART */

	const unsigned eng = 17;

	unsigned int i;

	unsigned char hub_ip = 0;



	hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?

		   GC_HWIP : MMHUB_HWIP;



	spin_lock(&adev->gmc.invalidate_lock);

	/*
@@ -242,8 +246,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 
	if (use_semaphore) {

		for (i = 0; i < adev->usec_timeout; i++) {

			/* a read return value of 1 means semaphore acuqire */

			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +

					    hub->eng_distance * eng);

			tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +

					 hub->eng_distance * eng, hub_ip);



			if (tmp & 0x1)

				break;

			udelay(1);
@@ -253,7 +258,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 
			DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");

	}



	WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);

	WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +

			  hub->eng_distance * eng,

			  inv_req, hub_ip);



	/*

	 * Issue a dummy read to wait for the ACK register to be cleared
@@ -261,12 +268,14 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 
	 */

	if ((vmhub == AMDGPU_GFXHUB_0) &&

	    (adev->asic_type < CHIP_SIENNA_CICHLID))

		RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng);

		RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +

				  hub->eng_distance * eng, hub_ip);



	/* Wait for ACK with a delay.*/

	for (i = 0; i < adev->usec_timeout; i++) {

		tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +

				    hub->eng_distance * eng);

		tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +

				  hub->eng_distance * eng, hub_ip);



		tmp &= 1 << vmid;

		if (tmp)

			break;
@@ -280,8 +289,8 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 
		 * add semaphore release after invalidation,

		 * write with 0 means semaphore release

		 */

		WREG32_NO_KIQ(hub->vm_inv_eng0_sem +

			      hub->eng_distance * eng, 0);

		WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +

				  hub->eng_distance * eng, 0, hub_ip);



	spin_unlock(&adev->gmc.invalidate_lock);