Unverified Commit 6c9762a7 authored by Marco Felsch's avatar Marco Felsch Committed by Mark Brown
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ASoC: max98088: fix ni clock divider calculation 

The ni1/ni2 ratio formula [1] uses the pclk which is the prescaled mclk.
The max98088 datasheet [2] has no such formula but table-12 equals so
we can assume that it is the same for both devices.

While on it make use of DIV_ROUND_CLOSEST_ULL().

[1] https://datasheets.maximintegrated.com/en/ds/MAX98089.pdf; page 86
[2] https://datasheets.maximintegrated.com/en/ds/MAX98088.pdf;

 page 82

Signed-off-by: default avatarMarco Felsch <m.felsch@pengutronix.de>
Link: https://lore.kernel.org/r/20210423135402.32105-1-m.felsch@pengutronix.de


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 25c4a9b6

sound/soc/codecs/max98088.c

+11 −2
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ struct max98088_priv { 
	enum max98088_type devtype;

	struct max98088_pdata *pdata;

	struct clk *mclk;

	unsigned char mclk_prescaler;

	unsigned int sysclk;

	struct max98088_cdata dai[2];

	int eq_textcnt;
@@ -998,13 +999,16 @@ static int max98088_dai1_hw_params(struct snd_pcm_substream *substream, 
       /* Configure NI when operating as master */

       if (snd_soc_component_read(component, M98088_REG_14_DAI1_FORMAT)

               & M98088_DAI_MAS) {

               unsigned long pclk;



               if (max98088->sysclk == 0) {

                       dev_err(component->dev, "Invalid system clock frequency\n");

                       return -EINVAL;

               }

               ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)

                               * (unsigned long long int)rate;

               do_div(ni, (unsigned long long int)max98088->sysclk);

               pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);

               ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);

               snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,

                       (ni >> 8) & 0x7F);

               snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
@@ -1065,13 +1069,16 @@ static int max98088_dai2_hw_params(struct snd_pcm_substream *substream, 
       /* Configure NI when operating as master */

       if (snd_soc_component_read(component, M98088_REG_1C_DAI2_FORMAT)

               & M98088_DAI_MAS) {

               unsigned long pclk;



               if (max98088->sysclk == 0) {

                       dev_err(component->dev, "Invalid system clock frequency\n");

                       return -EINVAL;

               }

               ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)

                               * (unsigned long long int)rate;

               do_div(ni, (unsigned long long int)max98088->sysclk);

               pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);

               ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);

               snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,

                       (ni >> 8) & 0x7F);

               snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
@@ -1113,8 +1120,10 @@ static int max98088_dai_set_sysclk(struct snd_soc_dai *dai, 
        */

       if ((freq >= 10000000) && (freq < 20000000)) {

               snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10);

               max98088->mclk_prescaler = 1;

       } else if ((freq >= 20000000) && (freq < 30000000)) {

               snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20);

               max98088->mclk_prescaler = 2;

       } else {

               dev_err(component->dev, "Invalid master clock frequency\n");

               return -EINVAL;