Commit 6cacdd46 authored by Devin Heitmueller's avatar Devin Heitmueller Committed by Mauro Carvalho Chehab
Browse files

[media] drxd: Run lindent across sources 



Take a first cleanup pass over the sources to bring them closer to the
Linux coding style.

Signed-off-by: default avatarDevin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 9b316d6b

drivers/media/dvb/frontends/drxd.h

+4 −5
Original line number Diff line number Diff line
@@ -27,8 +27,7 @@ 
#include <linux/types.h>

#include <linux/i2c.h>



struct drxd_config

{

struct drxd_config {

	u8 index;



	u8 pll_address;

drivers/media/dvb/frontends/drxd_firm.c

+782 −794
Original line number Diff line number Diff line
@@ -46,8 +46,7 @@ 
#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A

#define HI_TR_FUNC_SIZE 9	/* size of this function in instruction words */



u8_t DRXD_InitAtomicRead[] =

{

u8_t DRXD_InitAtomicRead[] = {

	WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),

	0x26, 0x00,		/* 0         -> ring.rdy;           */

	0x60, 0x04,		/* r0rami.dt -> ring.xba;           */
@@ -68,8 +67,7 @@ u8_t DRXD_InitAtomicRead[] = 
#define HI_RST_FUNC_SIZE 54	/* size of this function in instruction words */



/* D0 Version */

u8_t DRXD_HiI2cPatch_1[] =

{

u8_t DRXD_HiI2cPatch_1[] = {

	WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),

	0xC8, 0x07, 0x01, 0x00,	/* MASK      -> reg0.dt;                        */

	0xE0, 0x07, 0x15, 0x02,	/* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
@@ -115,10 +113,14 @@ u8_t DRXD_HiI2cPatch_1[] = 
	0x29, 0x00,		/* M_IC_CMD_RESET -> i2c.cmd;                   */

	0xF8, 0x07, 0x2F, 0x00,	/* 0x2F      -> jumps.ad;                       */



    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),

    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),

    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),

    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),

	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),

	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),

	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),

	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),

	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),

	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),

	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),

	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),



	/* Force quick and dirty reset */

	WR16(B_HI_CT_REG_COMM_STATE__A, 0),
@@ -126,8 +128,7 @@ u8_t DRXD_HiI2cPatch_1[] = 
};



/* D0,D1 Version */

u8_t DRXD_HiI2cPatch_3[] =

{

u8_t DRXD_HiI2cPatch_3[] = {

	WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),

	0xC8, 0x07, 0x03, 0x00,	/* MASK      -> reg0.dt;                        */

	0xE0, 0x07, 0x15, 0x02,	/* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
@@ -173,18 +174,21 @@ u8_t DRXD_HiI2cPatch_3[] = 
	0x29, 0x00,		/* M_IC_CMD_RESET -> i2c.cmd;                   */

	0xF8, 0x07, 0x2F, 0x00,	/* 0x2F      -> jumps.ad;                       */



    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),

    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),

    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),

    WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),

	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),

	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),

	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),

	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),

	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),

	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),

	WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),

	     (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),



	/* Force quick and dirty reset */

	WR16(B_HI_CT_REG_COMM_STATE__A, 0),

	END_OF_TABLE

};



u8_t DRXD_ResetCEFR[] =

{

u8_t DRXD_ResetCEFR[] = {

	WRBLOCK(CE_REG_FR_TREAL00__A, 57),

	0x52, 0x00,		/* CE_REG_FR_TREAL00__A */

	0x00, 0x00,		/* CE_REG_FR_TIMAG00__A */
@@ -251,9 +255,7 @@ u8_t DRXD_ResetCEFR[] = 
	END_OF_TABLE

};





u8_t DRXD_InitFEA2_1[] =

{

u8_t DRXD_InitFEA2_1[] = {

	WRBLOCK(FE_AD_REG_PD__A, 3),

	0x00, 0x00,		/* FE_AD_REG_PD__A          */

	0x01, 0x00,		/* FE_AD_REG_INVEXT__A      */
@@ -339,8 +341,7 @@ u8_t DRXD_InitFEA2_1[] = 
/*   WR16(FE_AG_REG_AG_AGC_SIO__A,  (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/

/*   WR16(FE_AG_REG_AG_PWD__A        ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/



u8_t DRXD_InitFEA2_2[] =

{

u8_t DRXD_InitFEA2_2[] = {

	WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),

	WR16(FE_AG_REG_FGM_WRI__A, 48),

	/* Activate measurement, activate scale */
@@ -358,8 +359,7 @@ u8_t DRXD_InitFEA2_2[] = 
	END_OF_TABLE

};



u8_t DRXD_InitFEB1_1[] =

{

u8_t DRXD_InitFEB1_1[] = {

	WR16(B_FE_AD_REG_PD__A, 0x0000),

	WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),

	WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
@@ -373,6 +373,7 @@ u8_t DRXD_InitFEB1_1[] = 
	WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),

	END_OF_TABLE

};



	/* with PGA */

/*      WR16(B_FE_AG_REG_AG_PGA_MODE__A   , 0x0000, 0x0000); */

       /* without PGA */
@@ -381,8 +382,7 @@ u8_t DRXD_InitFEB1_1[] = 
									     /*   WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */

/*   WR16(B_FE_AG_REG_AG_PWD__A    ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/



u8_t DRXD_InitFEB1_2[] =

{

u8_t DRXD_InitFEB1_2[] = {

	WR16(B_FE_COMM_EXEC__A, 0x0001),



	/* RF-AGC setup */
@@ -404,8 +404,7 @@ u8_t DRXD_InitFEB1_2[] = 
	END_OF_TABLE

};



u8_t DRXD_InitCPA2[] =

{

u8_t DRXD_InitCPA2[] = {

	WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),

	0x07, 0x00,		/* CP_REG_BR_SPL_OFFSET__A  */

	0x0A, 0x00,		/* CP_REG_BR_STR_DEL__A     */
@@ -435,16 +434,13 @@ u8_t DRXD_InitCPA2[] = 
	END_OF_TABLE

};



u8_t DRXD_InitCPB1[] =

{

u8_t DRXD_InitCPB1[] = {

	WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),

	WR16(B_CP_COMM_EXEC__A, 0x0001),

	END_OF_TABLE

};





u8_t DRXD_InitCEA2[] =

{

u8_t DRXD_InitCEA2[] = {

	WRBLOCK(CE_REG_AVG_POW__A, 4),

	0x62, 0x00,		/* CE_REG_AVG_POW__A        */

	0x78, 0x00,		/* CE_REG_MAX_POW__A        */
@@ -482,22 +478,19 @@ u8_t DRXD_InitCEA2[] = 
	0x00, 0x00,		/* CE_REG_IR_STARTPOS__A          */

	0xFF, 0x00,		/* CE_REG_IR_NEXP_THRES__A        */





	WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),



	END_OF_TABLE

};



u8_t DRXD_InitCEB1[] =

{

u8_t DRXD_InitCEB1[] = {

	WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),

	WR16(B_CE_REG_FR_PM_SET__A, 0x000D),



	END_OF_TABLE

};



u8_t DRXD_InitEQA2[] =

{

u8_t DRXD_InitEQA2[] = {

	WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),

	0x1E, 0x00,		/* EQ_REG_OT_QNT_THRES0__A        */

	0x1F, 0x00,		/* EQ_REG_OT_QNT_THRES1__A        */
@@ -512,14 +505,12 @@ u8_t DRXD_InitEQA2[] = 
	END_OF_TABLE

};



u8_t DRXD_InitEQB1[] =

{

u8_t DRXD_InitEQB1[] = {

	WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),

	END_OF_TABLE

};



u8_t DRXD_ResetECRAM[] =

{

u8_t DRXD_ResetECRAM[] = {

	/* Reset packet sync bytes in EC_VD ram */

	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),

	WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
@@ -539,8 +530,7 @@ u8_t DRXD_ResetECRAM[] = 
	END_OF_TABLE

};



u8_t DRXD_InitECA2[] =

{

u8_t DRXD_InitECA2[] = {

	WRBLOCK(EC_SB_REG_CSI_HI__A, 6),

	0x1F, 0x00,		/* EC_SB_REG_CSI_HI__A            */

	0x1E, 0x00,		/* EC_SB_REG_CSI_LO__A            */
@@ -626,8 +616,7 @@ u8_t DRXD_InitECA2[] = 
	END_OF_TABLE

};



u8_t DRXD_InitECB1[] =

{

u8_t DRXD_InitECB1[] = {

	WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),

	WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),

	WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
@@ -682,8 +671,7 @@ u8_t DRXD_InitECB1[] = 
	END_OF_TABLE

};



u8_t DRXD_ResetECA2[] =

{

u8_t DRXD_ResetECA2[] = {



	WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),

	WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
@@ -754,8 +742,7 @@ u8_t DRXD_ResetECA2[] = 
	END_OF_TABLE

};



u8_t DRXD_InitSC[] =

{

u8_t DRXD_InitSC[] = {

	WR16(SC_COMM_EXEC__A, 0),

	WR16(SC_COMM_STATE__A, 0),
@@ -769,8 +756,7 @@ u8_t DRXD_InitSC[] = 


/* Diversity settings */



u8_t DRXD_InitDiversityFront[] =

{

u8_t DRXD_InitDiversityFront[] = {

	/* Start demod ********* RF in , diversity out **************************** */

	WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |

	     B_SC_RA_RAM_CONFIG_FREQSCAN__M),
@@ -800,17 +786,14 @@ u8_t DRXD_InitDiversityFront[] = 
	WR16(B_CC_REG_DIVERSITY__A, 0x0001),

	WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),

	WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |

				 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE |

				 B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ),



	     B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),



	/*    0x2a ), *//* CE to PASS mux */



	END_OF_TABLE

};



u8_t DRXD_InitDiversityEnd[] =

{

u8_t DRXD_InitDiversityEnd[] = {

	/* End demod *********** combining RF in and diversity in, MPEG TS out **** */

	/* disable near/far; switch on timing slave mode */

	WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
@@ -852,23 +835,34 @@ u8_t DRXD_InitDiversityEnd[] = 
	END_OF_TABLE

};



u8_t DRXD_DisableDiversity[] =

{

u8_t DRXD_DisableDiversity[] = {

	WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),

	WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),

   WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE ),

   WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE ),

   WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE ),

   WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE ),

   WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE ),

   WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE ),



   WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE ),

   WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE ),

   WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE ),

   WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE ),

   WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE ),

   WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE ),

	WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,

	     B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE),

	WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A,

	     B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE),

	WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A,

	     B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE),

	WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A,

	     B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE),

	WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A,

	     B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE),

	WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A,

	     B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE),



	WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A,

	     B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE),

	WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A,

	     B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE),

	WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A,

	     B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE),

	WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A,

	     B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE),

	WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A,

	     B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE),

	WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A,

	     B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE),



	WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),

	WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
@@ -876,31 +870,27 @@ u8_t DRXD_DisableDiversity[] = 
	WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),

	WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),





	WR16(B_CC_REG_DIVERSITY__A, 0x0000),

	WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT),	/* combining disabled */



	END_OF_TABLE

};



u8_t DRXD_StartDiversityFront[] =

{

u8_t DRXD_StartDiversityFront[] = {

	/* Start demod, RF in and diversity out, no combining */

	WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),

	WR16(B_FE_AD_REG_FDB_IN__A, 0x0),

	WR16(B_FE_AD_REG_INVEXT__A, 0x0),

	WR16(B_EQ_REG_COMM_MB__A, 0x12),	/* EQ to MB out */

	WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |	/* CE to PASS mux */

				 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE |

				 B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ),

	     B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),



	WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2),



	END_OF_TABLE

};



u8_t DRXD_StartDiversityEnd[] =

{

u8_t DRXD_StartDiversityEnd[] = {

	/* End demod, combining RF in and diversity in, MPEG TS out */

	WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),	/* disable impulse noise cruncher */

	WR16(B_FE_AD_REG_INVEXT__A, 0x0),	/* clock inversion (for sohard board) */
@@ -908,14 +898,12 @@ u8_t DRXD_StartDiversityEnd[] = 


	WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON |	/* org = 0x81 combining enabled */

	     B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |

				 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |

				 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC ),

	     B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC),



	END_OF_TABLE

};



u8_t DRXD_DiversityDelay8MHZ[] =

{

u8_t DRXD_DiversityDelay8MHZ[] = {

	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),

	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),

	WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),

drivers/media/dvb/frontends/drxd_firm.h

+3 −5
Original line number Diff line number Diff line
@@ -65,7 +65,6 @@ typedef unsigned long u32_t; 


#define DRXD_SCAN_TIMEOUT    (650)





#define DRXD_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)

#define DRXD_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)

#define DRXD_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
@@ -78,7 +77,6 @@ typedef unsigned long u32_t; 
#define DIFF_TARGET           (4)

#define DIFF_MARGIN           (1)





extern u8_t DRXD_InitAtomicRead[];

extern u8_t DRXD_HiI2cPatch_1[];

extern u8_t DRXD_HiI2cPatch_3[];

drivers/media/dvb/frontends/drxd_hard.c

+1030 −1081

File changed.

Preview size limit exceeded, changes collapsed.

drivers/media/dvb/frontends/drxd_map_firm.h

+10 −1800

File changed.

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