Unverified Commit 6d243f89 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'stm32-dt-for-v6.1-1' of... 

Merge tag 'stm32-dt-for-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt

STM32 DT for v6.1, round 1

Highlights:
----------

- MPU:
  - General:
    - Add I2C support (5 instances) on STM32MP13.
    - Add SPI support (5 instabces) on STM32MP13.
    - Add timer interrupts support on STM32MP15.

  - ST boards:
    - Enable I2C1 and I2C5 on stm32mp135f-dk board.
    - Add SPI5 on stm32mp135f-dk board but disabled as only available on
      the GPIO expansion connector.

  - ARGON:
    - Remove spidev node as not used by the code.

* tag 'stm32-dt-for-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  ARM: dts: stm32: argon: remove spidev node
  ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi
  ARM: dts: stm32: Fix typo in license text for Engicam boards
  ARM: dts: stm32: Add timer interrupts on stm32mp15
  ARM: dts: stm32: add pinctrl and disabled spi5 node in stm32mp135f-dk
  ARM: dts: stm32: add spi nodes into stm32mp131.dtsi
  ARM: dts: stm32: enable i2c1 and i2c5 on stm32mp135f-dk.dts
  ARM: dts: stm32: add i2c nodes into stm32mp131.dtsi

Link: https://lore.kernel.org/r/d80afc20-2745-24a2-ab70-a5a03439bd50@foss.st.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents b68ec116 04c26c5a

arch/arm/boot/dts/stm32mp13-pinctrl.dtsi

+57 −0
Original line number Diff line number Diff line
@@ -6,6 +6,40 @@ 
#include <dt-bindings/pinctrl/stm32-pinfunc.h>



&pinctrl {

	i2c1_pins_a: i2c1-0 {

		pins {

			pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */

				 <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */

			bias-disable;

			drive-open-drain;

			slew-rate = <0>;

		};

	};



	i2c1_sleep_pins_a: i2c1-sleep-0 {

		pins {

			pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */

				 <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */

		};

	};



	i2c5_pins_a: i2c5-0 {

		pins {

			pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */

				 <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */

			bias-disable;

			drive-open-drain;

			slew-rate = <0>;

		};

	};



	i2c5_sleep_pins_a: i2c5-sleep-0 {

		pins {

			pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */

				 <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */

		};

	};



	sdmmc1_b4_pins_a: sdmmc1-b4-0 {

		pins {

			pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -108,6 +142,29 @@ pins { 
		};

	};



	spi5_pins_a: spi5-0 {

		pins1 {

			pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */

				 <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */

			bias-disable;

			drive-push-pull;

			slew-rate = <1>;

		};



		pins2 {

			pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */

			bias-disable;

		};

	};



	spi5_sleep_pins_a: spi5-sleep-0 {

		pins {

			pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */

				 <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */

				 <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */

		};

	};



	uart4_pins_a: uart4-0 {

		pins1 {

			pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */

arch/arm/boot/dts/stm32mp131.dtsi

+160 −0
Original line number Diff line number Diff line
@@ -97,6 +97,34 @@ scmi_shm: scmi-sram@0 { 
			};

		};



		spi2: spi@4000b000 {

			compatible = "st,stm32h7-spi";

			reg = <0x4000b000 0x400>;

			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc SPI2_K>;

			resets = <&rcc SPI2_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			dmas = <&dmamux1 39 0x400 0x01>,

			       <&dmamux1 40 0x400 0x01>;

			dma-names = "rx", "tx";

			status = "disabled";

		};



		spi3: spi@4000c000 {

			compatible = "st,stm32h7-spi";

			reg = <0x4000c000 0x400>;

			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc SPI3_K>;

			resets = <&rcc SPI3_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			dmas = <&dmamux1 61 0x400 0x01>,

			       <&dmamux1 62 0x400 0x01>;

			dma-names = "rx", "tx";

			status = "disabled";

		};



		uart4: serial@40010000 {

			compatible = "st,stm32h7-uart";

			reg = <0x40010000 0x400>;
@@ -106,6 +134,56 @@ uart4: serial@40010000 { 
			status = "disabled";

		};



		i2c1: i2c@40012000 {

			compatible = "st,stm32mp13-i2c";

			reg = <0x40012000 0x400>;

			interrupt-names = "event", "error";

			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc I2C1_K>;

			resets = <&rcc I2C1_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			dmas = <&dmamux1 33 0x400 0x1>,

			       <&dmamux1 34 0x400 0x1>;

			dma-names = "rx", "tx";

			st,syscfg-fmp = <&syscfg 0x4 0x1>;

			i2c-analog-filter;

			status = "disabled";

		};



		i2c2: i2c@40013000 {

			compatible = "st,stm32mp13-i2c";

			reg = <0x40013000 0x400>;

			interrupt-names = "event", "error";

			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc I2C2_K>;

			resets = <&rcc I2C2_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			dmas = <&dmamux1 35 0x400 0x1>,

			       <&dmamux1 36 0x400 0x1>;

			dma-names = "rx", "tx";

			st,syscfg-fmp = <&syscfg 0x4 0x2>;

			i2c-analog-filter;

			status = "disabled";

		};



		spi1: spi@44004000 {

			compatible = "st,stm32h7-spi";

			reg = <0x44004000 0x400>;

			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc SPI1_K>;

			resets = <&rcc SPI1_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			dmas = <&dmamux1 37 0x400 0x01>,

			       <&dmamux1 38 0x400 0x01>;

			dma-names = "rx", "tx";

			status = "disabled";

		};



		dma1: dma-controller@48000000 {

			compatible = "st,stm32-dma";

			reg = <0x48000000 0x400>;
@@ -153,6 +231,88 @@ dmamux1: dma-router@48002000 { 
			dma-channels = <16>;

		};



		spi4: spi@4c002000 {

			compatible = "st,stm32h7-spi";

			reg = <0x4c002000 0x400>;

			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc SPI4_K>;

			resets = <&rcc SPI4_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			dmas = <&dmamux1 83 0x400 0x01>,

			       <&dmamux1 84 0x400 0x01>;

			dma-names = "rx", "tx";

			status = "disabled";

		};



		spi5: spi@4c003000 {

			compatible = "st,stm32h7-spi";

			reg = <0x4c003000 0x400>;

			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc SPI5_K>;

			resets = <&rcc SPI5_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			dmas = <&dmamux1 85 0x400 0x01>,

			       <&dmamux1 86 0x400 0x01>;

			dma-names = "rx", "tx";

			status = "disabled";

		};



		i2c3: i2c@4c004000 {

			compatible = "st,stm32mp13-i2c";

			reg = <0x4c004000 0x400>;

			interrupt-names = "event", "error";

			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc I2C3_K>;

			resets = <&rcc I2C3_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			dmas = <&dmamux1 73 0x400 0x1>,

			       <&dmamux1 74 0x400 0x1>;

			dma-names = "rx", "tx";

			st,syscfg-fmp = <&syscfg 0x4 0x4>;

			i2c-analog-filter;

			status = "disabled";

		};



		i2c4: i2c@4c005000 {

			compatible = "st,stm32mp13-i2c";

			reg = <0x4c005000 0x400>;

			interrupt-names = "event", "error";

			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc I2C4_K>;

			resets = <&rcc I2C4_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			dmas = <&dmamux1 75 0x400 0x1>,

			       <&dmamux1 76 0x400 0x1>;

			dma-names = "rx", "tx";

			st,syscfg-fmp = <&syscfg 0x4 0x8>;

			i2c-analog-filter;

			status = "disabled";

		};



		i2c5: i2c@4c006000 {

			compatible = "st,stm32mp13-i2c";

			reg = <0x4c006000 0x400>;

			interrupt-names = "event", "error";

			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc I2C5_K>;

			resets = <&rcc I2C5_R>;

			#address-cells = <1>;

			#size-cells = <0>;

			dmas = <&dmamux1 115 0x400 0x1>,

			       <&dmamux1 116 0x400 0x1>;

			dma-names = "rx", "tx";

			st,syscfg-fmp = <&syscfg 0x4 0x10>;

			i2c-analog-filter;

			status = "disabled";

		};



		rcc: rcc@50000000 {

			compatible = "st,stm32mp13-rcc", "syscon";

			reg = <0x50000000 0x1000>;

arch/arm/boot/dts/stm32mp135f-dk.dts

+33 −0
Original line number Diff line number Diff line
@@ -68,6 +68,32 @@ vdd_sd: vdd-sd { 
	};

};



&i2c1 {

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&i2c1_pins_a>;

	pinctrl-1 = <&i2c1_sleep_pins_a>;

	i2c-scl-rising-time-ns = <96>;

	i2c-scl-falling-time-ns = <3>;

	clock-frequency = <1000000>;

	status = "okay";

	/* spare dmas for other usage */

	/delete-property/dmas;

	/delete-property/dma-names;

};



&i2c5 {

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&i2c5_pins_a>;

	pinctrl-1 = <&i2c5_sleep_pins_a>;

	i2c-scl-rising-time-ns = <170>;

	i2c-scl-falling-time-ns = <5>;

	clock-frequency = <400000>;

	status = "okay";

	/* spare dmas for other usage */

	/delete-property/dmas;

	/delete-property/dma-names;

};



&iwdg2 {

	timeout-sec = <32>;

	status = "okay";
@@ -90,6 +116,13 @@ &sdmmc1 { 
	status = "okay";

};



&spi5 {

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&spi5_pins_a>;

	pinctrl-1 = <&spi5_sleep_pins_a>;

	status = "disabled";

};



&uart4 {

	pinctrl-names = "default";

	pinctrl-0 = <&uart4_pins_a>;

arch/arm/boot/dts/stm32mp15-pinctrl.dtsi

+33 −17
Original line number Diff line number Diff line
@@ -1261,7 +1261,7 @@ pins { 
	};



	qspi_bk1_pins_a: qspi-bk1-0 {

		pins1 {

		pins {

			pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */

				 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */

				 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
@@ -1270,12 +1270,6 @@ pins1 { 
			drive-push-pull;

			slew-rate = <1>;

		};

		pins2 {

			pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */

			bias-pull-up;

			drive-push-pull;

			slew-rate = <1>;

		};

	};



	qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
@@ -1283,13 +1277,12 @@ pins { 
			pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */

				 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */

				 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */

				 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */

				 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */

				 <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */

		};

	};



	qspi_bk2_pins_a: qspi-bk2-0 {

		pins1 {

		pins {

			pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */

				 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */

				 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
@@ -1298,7 +1291,34 @@ pins1 { 
			drive-push-pull;

			slew-rate = <1>;

		};

		pins2 {

	};



	qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {

		pins {

			pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */

				 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */

				 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */

				 <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */

		};

	};



	qspi_cs1_pins_a: qspi-cs1-0 {

		pins {

			pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */

			bias-pull-up;

			drive-push-pull;

			slew-rate = <1>;

		};

	};



	qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {

		pins {

			pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */

		};

	};



	qspi_cs2_pins_a: qspi-cs2-0 {

		pins {

			pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */

			bias-pull-up;

			drive-push-pull;
@@ -1306,13 +1326,9 @@ pins2 { 
		};

	};



	qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {

	qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 {

		pins {

			pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */

				 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */

				 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */

				 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */

				 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */

			pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */

		};

	};

arch/arm/boot/dts/stm32mp151.dtsi

+34 −0
Original line number Diff line number Diff line
@@ -127,6 +127,8 @@ timers2: timer@40000000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40000000 0x400>;

			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM2_K>;

			clock-names = "int";

			dmas = <&dmamux1 18 0x400 0x1>,
@@ -160,6 +162,8 @@ timers3: timer@40001000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40001000 0x400>;

			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM3_K>;

			clock-names = "int";

			dmas = <&dmamux1 23 0x400 0x1>,
@@ -194,6 +198,8 @@ timers4: timer@40002000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40002000 0x400>;

			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM4_K>;

			clock-names = "int";

			dmas = <&dmamux1 29 0x400 0x1>,
@@ -226,6 +232,8 @@ timers5: timer@40003000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40003000 0x400>;

			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM5_K>;

			clock-names = "int";

			dmas = <&dmamux1 55 0x400 0x1>,
@@ -260,6 +268,8 @@ timers6: timer@40004000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40004000 0x400>;

			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM6_K>;

			clock-names = "int";

			dmas = <&dmamux1 69 0x400 0x1>;
@@ -278,6 +288,8 @@ timers7: timer@40005000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40005000 0x400>;

			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM7_K>;

			clock-names = "int";

			dmas = <&dmamux1 70 0x400 0x1>;
@@ -296,6 +308,8 @@ timers12: timer@40006000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40006000 0x400>;

			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM12_K>;

			clock-names = "int";

			status = "disabled";
@@ -318,6 +332,8 @@ timers13: timer@40007000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40007000 0x400>;

			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM13_K>;

			clock-names = "int";

			status = "disabled";
@@ -340,6 +356,8 @@ timers14: timer@40008000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x40008000 0x400>;

			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM14_K>;

			clock-names = "int";

			status = "disabled";
@@ -623,6 +641,11 @@ timers1: timer@44000000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x44000000 0x400>;

			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "brk", "up", "trg-com", "cc";

			clocks = <&rcc TIM1_K>;

			clock-names = "int";

			dmas = <&dmamux1 11 0x400 0x1>,
@@ -659,6 +682,11 @@ timers8: timer@44001000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x44001000 0x400>;

			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "brk", "up", "trg-com", "cc";

			clocks = <&rcc TIM8_K>;

			clock-names = "int";

			dmas = <&dmamux1 47 0x400 0x1>,
@@ -746,6 +774,8 @@ timers15: timer@44006000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x44006000 0x400>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM15_K>;

			clock-names = "int";

			dmas = <&dmamux1 105 0x400 0x1>,
@@ -773,6 +803,8 @@ timers16: timer@44007000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x44007000 0x400>;

			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM16_K>;

			clock-names = "int";

			dmas = <&dmamux1 109 0x400 0x1>,
@@ -797,6 +829,8 @@ timers17: timer@44008000 { 
			#size-cells = <0>;

			compatible = "st,stm32-timers";

			reg = <0x44008000 0x400>;

			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "global";

			clocks = <&rcc TIM17_K>;

			clock-names = "int";

			dmas = <&dmamux1 111 0x400 0x1>,