Commit 6f4c23e7 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: drop scaler config from plane state 



Scaler and pixel_ext configuration does not contain a long living state,
it is used only during plane update, so remove these two fields from
dpu_plane_state and allocate them on stack.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Link: https://lore.kernel.org/r/20211201225140.2481577-2-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 8a3b4c17

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

+26 −33
Original line number Diff line number Diff line
@@ -536,14 +536,12 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, 
		struct dpu_plane_state *pstate,

		uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,

		struct dpu_hw_scaler3_cfg *scale_cfg,

		struct dpu_hw_pixel_ext *pixel_ext,

		const struct dpu_format *fmt,

		uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)

{

	uint32_t i;



	memset(scale_cfg, 0, sizeof(*scale_cfg));

	memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext));



	scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =

		mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);

	scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
@@ -582,9 +580,9 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, 
			scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;

		}



		pstate->pixel_ext.num_ext_pxls_top[i] =

		pixel_ext->num_ext_pxls_top[i] =

			scale_cfg->src_height[i];

		pstate->pixel_ext.num_ext_pxls_left[i] =

		pixel_ext->num_ext_pxls_left[i] =

			scale_cfg->src_width[i];

	}

	if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
@@ -662,6 +660,11 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, 
		struct dpu_hw_pipe_cfg *pipe_cfg)

{

	const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);

	struct dpu_hw_scaler3_cfg scaler3_cfg;

	struct dpu_hw_pixel_ext pixel_ext;



	memset(&scaler3_cfg, 0, sizeof(scaler3_cfg));

	memset(&pixel_ext, 0, sizeof(pixel_ext));



	/* don't chroma subsample if decimating */

	/* update scaler. calculate default config for QSEED3 */
@@ -670,8 +673,23 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, 
			drm_rect_height(&pipe_cfg->src_rect),

			drm_rect_width(&pipe_cfg->dst_rect),

			drm_rect_height(&pipe_cfg->dst_rect),

			&pstate->scaler3_cfg, fmt,

			&scaler3_cfg, &pixel_ext, fmt,

			info->hsub, info->vsub);



	if (pdpu->pipe_hw->ops.setup_pe)

		pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,

				&pixel_ext);



	/**

	 * when programmed in multirect mode, scalar block will be

	 * bypassed. Still we need to update alpha and bitwidth

	 * ONLY for RECT0

	 */

	if (pdpu->pipe_hw->ops.setup_scaler &&

			pstate->multirect_index != DPU_SSPP_RECT_1)

		pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,

				pipe_cfg, &pixel_ext,

				&scaler3_cfg);

}



/**
@@ -712,7 +730,6 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, 
			drm_rect_width(&pipe_cfg.dst_rect);

		pipe_cfg.src_rect.y2 =

			drm_rect_height(&pipe_cfg.dst_rect);

		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);



		if (pdpu->pipe_hw->ops.setup_format)

			pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw,
@@ -724,15 +741,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, 
					&pipe_cfg,

					pstate->multirect_index);



		if (pdpu->pipe_hw->ops.setup_pe)

			pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,

					&pstate->pixel_ext);



		if (pdpu->pipe_hw->ops.setup_scaler &&

				pstate->multirect_index != DPU_SSPP_RECT_1)

			pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,

					&pipe_cfg, &pstate->pixel_ext,

					&pstate->scaler3_cfg);

		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg);

	}



	return 0;
@@ -1129,8 +1138,6 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 


	pipe_cfg.dst_rect = state->dst;



	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);



	/* override for color fill */

	if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {

		/* skip remaining processing on color fill */
@@ -1143,21 +1150,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) 
				pstate->multirect_index);

	}



	if (pdpu->pipe_hw->ops.setup_pe &&

			(pstate->multirect_index != DPU_SSPP_RECT_1))

		pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw,

				&pstate->pixel_ext);



	/**

	 * when programmed in multirect mode, scalar block will be

	 * bypassed. Still we need to update alpha and bitwidth

	 * ONLY for RECT0

	 */

	if (pdpu->pipe_hw->ops.setup_scaler &&

			pstate->multirect_index != DPU_SSPP_RECT_1)

		pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw,

				&pipe_cfg, &pstate->pixel_ext,

				&pstate->scaler3_cfg);

	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg);



	if (pdpu->pipe_hw->ops.setup_multirect)

		pdpu->pipe_hw->ops.setup_multirect(

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h

+0 −6
Original line number Diff line number Diff line
@@ -23,8 +23,6 @@ 
 * @multirect_index: index of the rectangle of SSPP

 * @multirect_mode: parallel or time multiplex multirect mode

 * @pending:	whether the current update is still pending

 * @scaler3_cfg: configuration data for scaler3

 * @pixel_ext: configuration data for pixel extensions

 * @plane_fetch_bw: calculated BW per plane

 * @plane_clk: calculated clk per plane

 */
@@ -37,10 +35,6 @@ struct dpu_plane_state { 
	uint32_t multirect_mode;

	bool pending;



	/* scaler configuration */

	struct dpu_hw_scaler3_cfg scaler3_cfg;

	struct dpu_hw_pixel_ext pixel_ext;



	u64 plane_fetch_bw;

	u64 plane_clk;

};