Loading arch/arm/boot/dts/imx7d.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -20,6 +20,7 @@ cpu1: cpu@1 { reg = <1>; clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; cpu-idle-states = <&cpu_sleep_wait>; }; }; Loading arch/arm/boot/dts/imx7s.dtsi +14 −0 Original line number Diff line number Diff line Loading @@ -54,6 +54,19 @@ cpus { #address-cells = <1>; #size-cells = <0>; idle-states { entry-method = "psci"; cpu_sleep_wait: cpu-sleep-wait { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; local-timer-stop; entry-latency-us = <100>; exit-latency-us = <50>; min-residency-us = <1000>; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; Loading @@ -61,6 +74,7 @@ cpu0: cpu@0 { clock-frequency = <792000000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; cpu-idle-states = <&cpu_sleep_wait>; }; }; Loading Loading
arch/arm/boot/dts/imx7d.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -20,6 +20,7 @@ cpu1: cpu@1 { reg = <1>; clock-frequency = <996000000>; operating-points-v2 = <&cpu0_opp_table>; cpu-idle-states = <&cpu_sleep_wait>; }; }; Loading
arch/arm/boot/dts/imx7s.dtsi +14 −0 Original line number Diff line number Diff line Loading @@ -54,6 +54,19 @@ cpus { #address-cells = <1>; #size-cells = <0>; idle-states { entry-method = "psci"; cpu_sleep_wait: cpu-sleep-wait { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; local-timer-stop; entry-latency-us = <100>; exit-latency-us = <50>; min-residency-us = <1000>; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; Loading @@ -61,6 +74,7 @@ cpu0: cpu@0 { clock-frequency = <792000000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; cpu-idle-states = <&cpu_sleep_wait>; }; }; Loading