Commit 7092432e authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: drop soc15_set_ip_blocks() 



No longer used since IP enumeration is now driven by
amdgpu IP discovery code.

Acked-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0f3d2b68

drivers/gpu/drm/amd/amdgpu/soc15.c

+0 −179
Original line number Diff line number Diff line
@@ -780,185 +780,6 @@ void soc15_set_virt_ops(struct amdgpu_device *adev) 
	soc15_reg_base_init(adev);

}



int soc15_set_ip_blocks(struct amdgpu_device *adev)

{

	/* for bare metal case */

	if (!amdgpu_sriov_vf(adev))

		soc15_reg_base_init(adev);



	if (adev->flags & AMD_IS_APU) {

		adev->nbio.funcs = &nbio_v7_0_funcs;

		adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;

	} else if (adev->asic_type == CHIP_VEGA20 ||

		   adev->asic_type == CHIP_ARCTURUS ||

		   adev->asic_type == CHIP_ALDEBARAN) {

		adev->nbio.funcs = &nbio_v7_4_funcs;

		adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;

	} else {

		adev->nbio.funcs = &nbio_v6_1_funcs;

		adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;

	}

	adev->hdp.funcs = &hdp_v4_0_funcs;



	if (adev->asic_type == CHIP_VEGA20 ||

	    adev->asic_type == CHIP_ARCTURUS ||

	    adev->asic_type == CHIP_ALDEBARAN)

		adev->df.funcs = &df_v3_6_funcs;

	else

		adev->df.funcs = &df_v1_7_funcs;



	if (adev->asic_type == CHIP_VEGA20 ||

	    adev->asic_type == CHIP_ARCTURUS)

		adev->smuio.funcs = &smuio_v11_0_funcs;

	else if (adev->asic_type == CHIP_ALDEBARAN)

		adev->smuio.funcs = &smuio_v13_0_funcs;

	else

		adev->smuio.funcs = &smuio_v9_0_funcs;



	adev->rev_id = soc15_get_rev_id(adev);



	switch (adev->asic_type) {

	case CHIP_VEGA10:

	case CHIP_VEGA12:

	case CHIP_VEGA20:

		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);



		/* For Vega10 SR-IOV, PSP need to be initialized before IH */

		if (amdgpu_sriov_vf(adev)) {

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {

				if (adev->asic_type == CHIP_VEGA20)

					amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

				else

					amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);

			}

			if (adev->asic_type == CHIP_VEGA20)

				amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);

			else

				amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);

		} else {

			if (adev->asic_type == CHIP_VEGA20)

				amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);

			else

				amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {

				if (adev->asic_type == CHIP_VEGA20)

					amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

				else

					amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);

			}

		}

		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);

		if (is_support_sw_smu(adev)) {

			if (!amdgpu_sriov_vf(adev))

				amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);

		} else {

			amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);

		}

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {

			amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);

			amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);

		}

		break;

	case CHIP_RAVEN:

		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);

		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

			amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);

		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

		else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);

		break;

	case CHIP_ARCTURUS:

		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);



		if (amdgpu_sriov_vf(adev)) {

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

			amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);

		} else {

			amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		}



		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);

		amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);



		if (amdgpu_sriov_vf(adev)) {

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

				amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);

		} else {

			amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);

		}

		if (!amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);

		break;

	case CHIP_RENOIR:

		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);

		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

			amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);

		amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);

		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);

#if defined(CONFIG_DRM_AMD_DC)

                else if (amdgpu_device_has_dc_support(adev))

			amdgpu_device_ip_block_add(adev, &dm_ip_block);

#endif

		amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);

		amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);

		break;

	case CHIP_ALDEBARAN:

		amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);



		if (amdgpu_sriov_vf(adev)) {

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

				amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);

			amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);

		} else {

			amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

				amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);

		}



		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);



		amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);

		amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);

		amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);

		break;

	default:

		return -EINVAL;

	}



	return 0;

}



static bool soc15_need_full_reset(struct amdgpu_device *adev)

{

	/* change this when we implement soft reset */

drivers/gpu/drm/amd/amdgpu/soc15.h

+0 −1
Original line number Diff line number Diff line
@@ -102,7 +102,6 @@ struct soc15_ras_field_entry { 
void soc15_grbm_select(struct amdgpu_device *adev,

		    u32 me, u32 pipe, u32 queue, u32 vmid);

void soc15_set_virt_ops(struct amdgpu_device *adev);

int soc15_set_ip_blocks(struct amdgpu_device *adev);



void soc15_program_register_sequence(struct amdgpu_device *adev,

					     const struct soc15_reg_golden *registers,