Commit 70b9bd39 authored by Ahsan Atta's avatar Ahsan Atta Committed by Herbert Xu
Browse files

crypto: qat - num_rings_per_bank is device dependent 



This change is to allow support for QAT devices that may not have 16
rings per bank.
The rings structure in bank is allocated dynamically based on the number
of banks supported by a device.

Note that in the error path in adf_init_bank(), ring->inflights is set
to NULL after the free to silence a false positive double free reported
by clang scan-build.

Signed-off-by: default avatarAhsan Atta <ahsan.atta@intel.com>
Co-developed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: default avatarFiona Trahe <fiona.trahe@intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 7b07ed50

drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c

+1 −0
Original line number Diff line number Diff line
@@ -176,6 +176,7 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data) 
	hw_data->dev_class = &c3xxx_class;

	hw_data->instance_id = c3xxx_class.instances++;

	hw_data->num_banks = ADF_C3XXX_ETR_MAX_BANKS;

	hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;

	hw_data->num_accel = ADF_C3XXX_MAX_ACCELERATORS;

	hw_data->num_logical_accel = 1;

	hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES;

drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c

+1 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data) 
{

	hw_data->dev_class = &c3xxxiov_class;

	hw_data->num_banks = ADF_C3XXXIOV_ETR_MAX_BANKS;

	hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;

	hw_data->num_accel = ADF_C3XXXIOV_MAX_ACCELERATORS;

	hw_data->num_logical_accel = 1;

	hw_data->num_engines = ADF_C3XXXIOV_MAX_ACCELENGINES;

drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c

+1 −0
Original line number Diff line number Diff line
@@ -186,6 +186,7 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data) 
	hw_data->dev_class = &c62x_class;

	hw_data->instance_id = c62x_class.instances++;

	hw_data->num_banks = ADF_C62X_ETR_MAX_BANKS;

	hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;

	hw_data->num_accel = ADF_C62X_MAX_ACCELERATORS;

	hw_data->num_logical_accel = 1;

	hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES;

drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c

+1 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data) 
{

	hw_data->dev_class = &c62xiov_class;

	hw_data->num_banks = ADF_C62XIOV_ETR_MAX_BANKS;

	hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;

	hw_data->num_accel = ADF_C62XIOV_MAX_ACCELERATORS;

	hw_data->num_logical_accel = 1;

	hw_data->num_engines = ADF_C62XIOV_MAX_ACCELENGINES;

drivers/crypto/qat/qat_common/adf_accel_devices.h

+3 −0
Original line number Diff line number Diff line
@@ -139,6 +139,7 @@ struct adf_hw_device_data { 
	u16 tx_rings_mask;

	u8 tx_rx_gap;

	u8 num_banks;

	u8 num_rings_per_bank;

	u8 num_accel;

	u8 num_logical_accel;

	u8 num_engines;
@@ -156,6 +157,8 @@ struct adf_hw_device_data { 
#define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)

#define GET_HW_DATA(accel_dev) (accel_dev->hw_device)

#define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)

#define GET_NUM_RINGS_PER_BANK(accel_dev) \

	GET_HW_DATA(accel_dev)->num_rings_per_bank

#define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)

#define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev