Commit 70c459d9 authored by Carlos Bilbao's avatar Carlos Bilbao Committed by Borislav Petkov
Browse files

x86/mce: Simplify AMD severity grading logic



The MCE handler needs to understand the severity of the machine errors to
act accordingly. Simplify the AMD grading logic following a logic that
closely resembles the descriptions of the public PPR documents. This will
help include more fine-grained grading of errors in the future.

  [ bp: Touchups. ]

Signed-off-by: default avatarCarlos Bilbao <carlos.bilbao@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Link: https://lore.kernel.org/r/20220405183212.354606-2-carlos.bilbao@amd.com
parent e5f28623
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+36 −65
Original line number Diff line number Diff line
@@ -301,85 +301,56 @@ static noinstr int error_context(struct mce *m, struct pt_regs *regs)
	}
}

static __always_inline int mce_severity_amd_smca(struct mce *m, enum context err_ctx)
/* See AMD PPR(s) section Machine Check Error Handling. */
static noinstr int mce_severity_amd(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp)
{
	u64 mcx_cfg;
	int ret;

	/*
	 * We need to look at the following bits:
	 * - "succor" bit (data poisoning support), and
	 * - TCC bit (Task Context Corrupt)
	 * in MCi_STATUS to determine error severity.
	 * Default return value: Action required, the error must be handled
	 * immediately.
	 */
	if (!mce_flags.succor)
		return MCE_PANIC_SEVERITY;
	ret = MCE_AR_SEVERITY;

	mcx_cfg = mce_rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(m->bank));

	/* TCC (Task context corrupt). If set and if IN_KERNEL, panic. */
	if ((mcx_cfg & MCI_CONFIG_MCAX) &&
	    (m->status & MCI_STATUS_TCC) &&
	    (err_ctx == IN_KERNEL))
		return MCE_PANIC_SEVERITY;
	/* Processor Context Corrupt, no need to fumble too much, die! */
	if (m->status & MCI_STATUS_PCC) {
		ret = MCE_PANIC_SEVERITY;
		goto out;
	}

	 /* ...otherwise invoke hwpoison handler. */
	return MCE_AR_SEVERITY;
	if (m->status & MCI_STATUS_DEFERRED) {
		ret = MCE_DEFERRED_SEVERITY;
		goto out;
	}

	/*
 * See AMD Error Scope Hierarchy table in a newer BKDG. For example
 * 49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features"
	 * If the UC bit is not set, the system either corrected or deferred
	 * the error. No action will be required after logging the error.
	 */
static noinstr int mce_severity_amd(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp)
{
	enum context ctx = error_context(m, regs);

	/* Processor Context Corrupt, no need to fumble too much, die! */
	if (m->status & MCI_STATUS_PCC)
		return MCE_PANIC_SEVERITY;

	if (m->status & MCI_STATUS_UC) {

		if (ctx == IN_KERNEL)
			return MCE_PANIC_SEVERITY;
	if (!(m->status & MCI_STATUS_UC)) {
		ret = MCE_KEEP_SEVERITY;
		goto out;
	}

	/*
		 * On older systems where overflow_recov flag is not present, we
		 * should simply panic if an error overflow occurs. If
		 * overflow_recov flag is present and set, then software can try
		 * to at least kill process to prolong system operation.
	 * On MCA overflow, without the MCA overflow recovery feature the
	 * system will not be able to recover, panic.
	 */
		if (mce_flags.overflow_recov) {
			if (mce_flags.smca)
				return mce_severity_amd_smca(m, ctx);

			/* kill current process */
			return MCE_AR_SEVERITY;
		} else {
			/* at least one error was not logged */
			if (m->status & MCI_STATUS_OVER)
				return MCE_PANIC_SEVERITY;
	if ((m->status & MCI_STATUS_OVER) && !mce_flags.overflow_recov) {
		ret = MCE_PANIC_SEVERITY;
		goto out;
	}

		/*
		 * For any other case, return MCE_UC_SEVERITY so that we log the
		 * error and exit #MC handler.
		 */
		return MCE_UC_SEVERITY;
	if (!mce_flags.succor) {
		ret = MCE_PANIC_SEVERITY;
		goto out;
	}

	/*
	 * deferred error: poll handler catches these and adds to mce_ring so
	 * memory-failure can take recovery actions.
	 */
	if (m->status & MCI_STATUS_DEFERRED)
		return MCE_DEFERRED_SEVERITY;
	if (error_context(m, regs) == IN_KERNEL)
		ret = MCE_PANIC_SEVERITY;

	/*
	 * corrected error: poll handler catches these and passes responsibility
	 * of decoding the error to EDAC
	 */
	return MCE_KEEP_SEVERITY;
out:
	return ret;
}

static noinstr int mce_severity_intel(struct mce *m, struct pt_regs *regs, char **msg, bool is_excp)