Commit 7229bd6f authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu/vcn: update clock gate setting for VCN 4.0.3 



Update clock gate setting.

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d4ad24a0

drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

+16 −14
Original line number Diff line number Diff line
@@ -424,12 +424,13 @@ static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indir 
static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_device *adev)

{

	uint32_t data;

	int inst_idx = 0;



	/* VCN disable CGC */

	data = RREG32_SOC15(VCN, 0, regUVD_CGC_CTRL);

	if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)

		data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

	else

		return;



	/* VCN disable CGC */

	data = RREG32_SOC15(VCN, inst_idx, regUVD_CGC_CTRL);

	data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;

	data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

	data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
@@ -517,10 +518,10 @@ static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, 
{

	uint32_t reg_data = 0;



	/* enable sw clock gating control */

	if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)

		reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

	else

		return;



	/* enable sw clock gating control */

	reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

	reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

	reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
@@ -563,12 +564,13 @@ static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, 
static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_device *adev)

{

	uint32_t data;

	int inst_idx = 0;



	/* enable VCN CGC */

	data = RREG32_SOC15(VCN, 0, regUVD_CGC_CTRL);

	if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)

		data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

	else

		return;



	/* enable VCN CGC */

	data = RREG32_SOC15(VCN, inst_idx, regUVD_CGC_CTRL);

	data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;

	data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;

	data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;