Commit 7389a5b8 authored by yipechai's avatar yipechai Committed by Alex Deucher
Browse files

drm/amdgpu: Removed redundant ras code 



Removed redundant ras code.

Signed-off-by: default avataryipechai <YiPeng.Chai@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarJohn Clements <john.clements@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 22d4ba53

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+19 −48
Original line number Diff line number Diff line
@@ -946,40 +946,25 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev, 
	if (!obj)

		return -EINVAL;



	block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);



	switch (info->head.block) {

	case AMDGPU_RAS_BLOCK__UMC:

	if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {

		amdgpu_ras_get_ecc_info(adev, &err_data);

		break;

	case AMDGPU_RAS_BLOCK__SDMA:

	case AMDGPU_RAS_BLOCK__GFX:

	case AMDGPU_RAS_BLOCK__MMHUB:

	} else {

		block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);

		if (!block_obj || !block_obj->hw_ops)   {

			dev_info(adev->dev, "%s doesn't config ras function \n",

					get_ras_block_str(&info->head));

			return -EINVAL;

		}



		if (block_obj->hw_ops->query_ras_error_count)

			block_obj->hw_ops->query_ras_error_count(adev, &err_data);



		if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||

		    (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||

		    (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {

				if (block_obj->hw_ops->query_ras_error_status)

					block_obj->hw_ops->query_ras_error_status(adev);

		break;

	case AMDGPU_RAS_BLOCK__PCIE_BIF:

	case AMDGPU_RAS_BLOCK__XGMI_WAFL:

	case AMDGPU_RAS_BLOCK__HDP:

	case AMDGPU_RAS_BLOCK__MCA:

		if (!block_obj || !block_obj->hw_ops)	{

			dev_info(adev->dev, "%s doesn't config ras function \n",

				get_ras_block_str(&info->head));

			return -EINVAL;

			}

		if (block_obj->hw_ops->query_ras_error_count)

			block_obj->hw_ops->query_ras_error_count(adev, &err_data);

		break;

	default:

		break;

	}



	obj->err_data.ue_count += err_data.ue_count;
@@ -1041,9 +1026,6 @@ int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 
	if (!amdgpu_ras_is_supported(adev, block))

		return -EINVAL;



	switch (block) {

	case AMDGPU_RAS_BLOCK__GFX:

	case AMDGPU_RAS_BLOCK__MMHUB:

	if (!block_obj || !block_obj->hw_ops)   {

		dev_info(adev->dev, "%s doesn't config ras function \n", ras_block_str(block));

		return -EINVAL;
@@ -1052,21 +1034,10 @@ int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, 
	if (block_obj->hw_ops->reset_ras_error_count)

		block_obj->hw_ops->reset_ras_error_count(adev);



	if ((block == AMDGPU_RAS_BLOCK__GFX) ||

	    (block == AMDGPU_RAS_BLOCK__MMHUB)) {

		if (block_obj->hw_ops->reset_ras_error_status)

			block_obj->hw_ops->reset_ras_error_status(adev);

		break;

	case AMDGPU_RAS_BLOCK__SDMA:

	case AMDGPU_RAS_BLOCK__HDP:

		if (!block_obj || !block_obj->hw_ops)	{

			dev_info(adev->dev, "%s doesn't config ras function \n", ras_block_str(block));

			return -EINVAL;

		}



		if (block_obj->hw_ops->reset_ras_error_count)

			block_obj->hw_ops->reset_ras_error_count(adev);

		break;

	default:

		break;

	}



	return 0;