Commit 74521205 authored by Robert Marko's avatar Robert Marko Committed by Bjorn Andersson
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clk: qcom: ipq8074: add PPE crypto clock 



The built-in PPE engine has a dedicated clock for the EIP-197 crypto
engine.

So, since the required clock currently missing add support for it.

Signed-off-by: default avatarRobert Marko <robimarko@gmail.com>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com
parent 90e6d290

drivers/clk/qcom/gcc-ipq8074.c

+19 −0
Original line number Diff line number Diff line
@@ -3182,6 +3182,24 @@ static struct clk_branch gcc_nss_ptp_ref_clk = { 
	},

};



static struct clk_branch gcc_crypto_ppe_clk = {

	.halt_reg = 0x68310,

	.halt_bit = 31,

	.clkr = {

		.enable_reg = 0x68310,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_crypto_ppe_clk",

			.parent_names = (const char *[]){

				"nss_ppe_clk_src"

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_nssnoc_ce_apb_clk = {

	.halt_reg = 0x6830c,

	.clkr = {
@@ -4644,6 +4662,7 @@ static struct clk_regmap *gcc_ipq8074_clks[] = { 
	[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,

	[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,

	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,

	[GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,

};



static const struct qcom_reset_map gcc_ipq8074_resets[] = {