Loading drivers/gpu/drm/nouveau/nvc0_grctx.c +3 −2 Original line number Diff line number Diff line Loading @@ -1783,10 +1783,11 @@ nvc0_grctx_generate(struct nouveau_channel *chan) nv_wr32(dev, 0x40587c, 0x00000000); if (1) { const u8 chipset_tp_max[] = { 16, 0, 0, 4, 8 }; const u8 chipset_tp_max[] = { 16, 4, 0, 4, 8, 0, 0, 0, 16, 0, 0, 0, 0, 0, 8, 0 }; u8 max = chipset_tp_max[dev_priv->chipset & 0x0f]; u8 tpnr[GPC_MAX]; u8 data[32]; u8 data[TP_MAX]; memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr)); memset(data, 0x1f, sizeof(data)); Loading Loading
drivers/gpu/drm/nouveau/nvc0_grctx.c +3 −2 Original line number Diff line number Diff line Loading @@ -1783,10 +1783,11 @@ nvc0_grctx_generate(struct nouveau_channel *chan) nv_wr32(dev, 0x40587c, 0x00000000); if (1) { const u8 chipset_tp_max[] = { 16, 0, 0, 4, 8 }; const u8 chipset_tp_max[] = { 16, 4, 0, 4, 8, 0, 0, 0, 16, 0, 0, 0, 0, 0, 8, 0 }; u8 max = chipset_tp_max[dev_priv->chipset & 0x0f]; u8 tpnr[GPC_MAX]; u8 data[32]; u8 data[TP_MAX]; memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr)); memset(data, 0x1f, sizeof(data)); Loading