Commit 757b3af8 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: add ih ip block for sienna_cichlid 



Update IH handling for sienna_cichlid

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0b3df16b

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

+17 −4
Original line number Diff line number Diff line
@@ -34,6 +34,9 @@ 


#define MAX_REARM_RETRY 10



#define mmIH_CHICKEN_Sienna_Cichlid                 0x018d

#define mmIH_CHICKEN_Sienna_Cichlid_BASE_IDX        0



static void navi10_ih_set_interrupt_funcs(struct amdgpu_device *adev);



/**
@@ -265,10 +268,20 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) 


	if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {

		if (ih->use_bus_addr) {

			switch (adev->asic_type) {

			case CHIP_SIENNA_CICHLID:

				ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);

				ih_chicken = REG_SET_FIELD(ih_chicken,

						IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);

				WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken);

				break;

			default:

				ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);

				ih_chicken = REG_SET_FIELD(ih_chicken,

						IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);

				WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);

				break;

			}

		}

	}

drivers/gpu/drm/amd/amdgpu/nv.c

+1 −0
Original line number Diff line number Diff line
@@ -486,6 +486,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
	case CHIP_SIENNA_CICHLID:

		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		break;

	default:

		return -EINVAL;