Commit 75df9e88 authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
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drm/amdgpu/gfx10: use per ctx CSA for ce metadata 



As MES requires per context preemption, use per context CSA address
for CE metadata to correctly enable context MCBP preemption.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c755f680

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+19 −9
Original line number Diff line number Diff line
@@ -8849,26 +8849,36 @@ static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 
{

	struct amdgpu_device *adev = ring->adev;

	struct v10_ce_ib_state ce_payload = {0};

	uint64_t csa_addr;

	uint64_t offset, ce_payload_gpu_addr;

	void *ce_payload_cpu_addr;

	int cnt;



	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;

	csa_addr = amdgpu_csa_vaddr(ring->adev);



	if (ring->is_mes_queue) {

		offset = offsetof(struct amdgpu_mes_ctx_meta_data,

				  gfx[0].gfx_meta_data) +

			offsetof(struct v10_gfx_meta_data, ce_payload);

		ce_payload_gpu_addr =

			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);

		ce_payload_cpu_addr =

			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);

	} else {

		offset = offsetof(struct v10_gfx_meta_data, ce_payload);

		ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;

		ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;

	}



	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));

	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |

				 WRITE_DATA_DST_SEL(8) |

				 WR_CONFIRM) |

				 WRITE_DATA_CACHE_POLICY(0));

	amdgpu_ring_write(ring, lower_32_bits(csa_addr +

			      offsetof(struct v10_gfx_meta_data, ce_payload)));

	amdgpu_ring_write(ring, upper_32_bits(csa_addr +

			      offsetof(struct v10_gfx_meta_data, ce_payload)));

	amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));

	amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));



	if (resume)

		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +

					   offsetof(struct v10_gfx_meta_data,

						    ce_payload),

		amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,

					   sizeof(ce_payload) >> 2);

	else

		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,