Commit 7741cced authored by Leo Liu's avatar Leo Liu Committed by Alex Deucher
Browse files

drm/amdgpu: expose vcn RB command 



Signed-off-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8c303c01

drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

+7 −0
Original line number Diff line number Diff line
@@ -30,6 +30,13 @@ 
#define AMDGPU_VCN_FIRMWARE_OFFSET	256

#define AMDGPU_VCN_MAX_ENC_RINGS	3



#define VCN_CMD_FENCE			0x00000000

#define VCN_CMD_TRAP			0x00000001

#define VCN_CMD_WRITE_REG		0x00000004

#define VCN_CMD_REG_READ_COND_WAIT	0x00000006

#define VCN_CMD_PACKET_START		0x0000000a

#define VCN_CMD_PACKET_END		0x0000000b



struct amdgpu_vcn {

	struct amdgpu_bo	*vcpu_bo;

	void			*cpu_addr;

drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

+4 −4
Original line number Diff line number Diff line
@@ -512,7 +512,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 
	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);

	amdgpu_ring_write(ring,

		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring, VCN_CMD_FENCE << 1);



	amdgpu_ring_write(ring,

		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
@@ -522,7 +522,7 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 
	amdgpu_ring_write(ring, 0);

	amdgpu_ring_write(ring,

		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

	amdgpu_ring_write(ring, 2);

	amdgpu_ring_write(ring, VCN_CMD_TRAP << 1);

}



/**
@@ -576,7 +576,7 @@ static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring, 
	amdgpu_ring_write(ring, data1);

	amdgpu_ring_write(ring,

		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

	amdgpu_ring_write(ring, 8);

	amdgpu_ring_write(ring, VCN_CMD_WRITE_REG << 1);

}



static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
@@ -593,7 +593,7 @@ static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, 
	amdgpu_ring_write(ring, mask);

	amdgpu_ring_write(ring,

		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));

	amdgpu_ring_write(ring, 12);

	amdgpu_ring_write(ring, VCN_CMD_REG_READ_COND_WAIT << 1);

}



static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,