Commit 77d7676a authored by Rasmus Villemoes's avatar Rasmus Villemoes Committed by Li Yang
Browse files

soc: fsl: qe: avoid ppc-specific io accessors 



In preparation for allowing to build QE support for architectures
other than PPC, replace the ppc-specific io accessors by the qe_io*
macros. Done via

$ spatch --sp-file io.cocci --in-place drivers/soc/fsl/qe/

where io.cocci is

@@
expression addr, val;
@@
- out_be32(addr, val)
+ qe_iowrite32be(val, addr)

@@
expression addr;
@@
- in_be32(addr)
+ qe_ioread32be(addr)

@@
expression addr, val;
@@
- out_be16(addr, val)
+ qe_iowrite16be(val, addr)

@@
expression addr;
@@
- in_be16(addr)
+ qe_ioread16be(addr)

@@
expression addr, val;
@@
- out_8(addr, val)
+ qe_iowrite8(val, addr)

@@
expression addr;
@@
- in_8(addr)
+ qe_ioread8(addr)

@@
expression addr, clr, set;
@@
- clrsetbits_be32(addr, clr, set)
+ qe_clrsetbits_be32(addr, clr, set)

@@
expression addr, clr, set;
@@
- clrsetbits_be16(addr, clr, set)
+ qe_clrsetbits_be16(addr, clr, set)

@@
expression addr, clr, set;
@@
- clrsetbits_8(addr, clr, set)
+ qe_clrsetbits_8(addr, clr, set)

@@
expression addr, set;
@@
- setbits32(addr, set)
+ qe_setbits_be32(addr, set)

@@
expression addr, set;
@@
- setbits16(addr, set)
+ qe_setbits_be16(addr, set)

@@
expression addr, set;
@@
- setbits8(addr, set)
+ qe_setbits_8(addr, set)

@@
expression addr, clr;
@@
- clrbits32(addr, clr)
+ qe_clrbits_be32(addr, clr)

@@
expression addr, clr;
@@
- clrbits16(addr, clr)
+ qe_clrbits_be16(addr, clr)

@@
expression addr, clr;
@@
- clrbits8(addr, clr)
+ qe_clrbits_8(addr, clr)

Reviewed-by: default avatarTimur Tabi <timur@kernel.org>
Signed-off-by: default avatarRasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: default avatarLi Yang <leoyang.li@nxp.com>
parent 6ac9b617

drivers/soc/fsl/qe/gpio.c

+19 −15
Original line number Diff line number Diff line
@@ -41,13 +41,13 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc) 
		container_of(mm_gc, struct qe_gpio_chip, mm_gc);

	struct qe_pio_regs __iomem *regs = mm_gc->regs;



	qe_gc->cpdata = in_be32(&regs->cpdata);

	qe_gc->cpdata = qe_ioread32be(&regs->cpdata);

	qe_gc->saved_regs.cpdata = qe_gc->cpdata;

	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);

	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);

	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);

	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);

	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);

	qe_gc->saved_regs.cpdir1 = qe_ioread32be(&regs->cpdir1);

	qe_gc->saved_regs.cpdir2 = qe_ioread32be(&regs->cpdir2);

	qe_gc->saved_regs.cppar1 = qe_ioread32be(&regs->cppar1);

	qe_gc->saved_regs.cppar2 = qe_ioread32be(&regs->cppar2);

	qe_gc->saved_regs.cpodr = qe_ioread32be(&regs->cpodr);

}



static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -56,7 +56,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio) 
	struct qe_pio_regs __iomem *regs = mm_gc->regs;

	u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);



	return !!(in_be32(&regs->cpdata) & pin_mask);

	return !!(qe_ioread32be(&regs->cpdata) & pin_mask);

}



static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
@@ -74,7 +74,7 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 
	else

		qe_gc->cpdata &= ~pin_mask;



	out_be32(&regs->cpdata, qe_gc->cpdata);

	qe_iowrite32be(qe_gc->cpdata, &regs->cpdata);



	spin_unlock_irqrestore(&qe_gc->lock, flags);

}
@@ -101,7 +101,7 @@ static void qe_gpio_set_multiple(struct gpio_chip *gc, 
		}

	}



	out_be32(&regs->cpdata, qe_gc->cpdata);

	qe_iowrite32be(qe_gc->cpdata, &regs->cpdata);



	spin_unlock_irqrestore(&qe_gc->lock, flags);

}
@@ -255,11 +255,15 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin) 
	spin_lock_irqsave(&qe_gc->lock, flags);



	if (second_reg) {

		clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);

		clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);

		qe_clrsetbits_be32(&regs->cpdir2, mask2,

				   sregs->cpdir2 & mask2);

		qe_clrsetbits_be32(&regs->cppar2, mask2,

				   sregs->cppar2 & mask2);

	} else {

		clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);

		clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);

		qe_clrsetbits_be32(&regs->cpdir1, mask2,

				   sregs->cpdir1 & mask2);

		qe_clrsetbits_be32(&regs->cppar1, mask2,

				   sregs->cppar1 & mask2);

	}



	if (sregs->cpdata & mask1)
@@ -267,8 +271,8 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin) 
	else

		qe_gc->cpdata &= ~mask1;



	out_be32(&regs->cpdata, qe_gc->cpdata);

	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);

	qe_iowrite32be(qe_gc->cpdata, &regs->cpdata);

	qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);



	spin_unlock_irqrestore(&qe_gc->lock, flags);

}

drivers/soc/fsl/qe/qe.c

+20 −18
Original line number Diff line number Diff line
@@ -112,7 +112,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) 


	spin_lock_irqsave(&qe_lock, flags);

	if (cmd == QE_RESET) {

		out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));

		qe_iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);

	} else {

		if (cmd == QE_ASSIGN_PAGE) {

			/* Here device is the SNUM, not sub-block */
@@ -129,14 +129,13 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input) 
				mcn_shift = QE_CR_MCN_NORMAL_SHIFT;

		}



		out_be32(&qe_immr->cp.cecdr, cmd_input);

		out_be32(&qe_immr->cp.cecr,

			 (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)

			  mcn_protocol << mcn_shift));

		qe_iowrite32be(cmd_input, &qe_immr->cp.cecdr);

		qe_iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),

			       &qe_immr->cp.cecr);

	}



	/* wait for the QE_CR_FLG to clear */

	ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,

	ret = spin_event_timeout((qe_ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,

				 100, 0);

	/* On timeout (e.g. failure), the expression will be false (ret == 0),

	   otherwise it will be true (ret == 1). */
@@ -230,7 +229,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier) 
	tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |

		QE_BRGC_ENABLE | div16;



	out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);

	qe_iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);



	return 0;

}
@@ -377,9 +376,10 @@ static int qe_sdma_init(void) 
			return -ENOMEM;

	}



	out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);

	out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |

		 (0x1 << QE_SDMR_CEN_SHIFT)));

	qe_iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK,

		       &sdma->sdebcr);

	qe_iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),

		       &sdma->sdmr);



	return 0;

}
@@ -417,14 +417,14 @@ static void qe_upload_microcode(const void *base, 
			"uploading microcode '%s'\n", ucode->id);



	/* Use auto-increment */

	out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |

		QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);

	qe_iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,

		       &qe_immr->iram.iadd);



	for (i = 0; i < be32_to_cpu(ucode->count); i++)

		out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));

		qe_iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);

	

	/* Set I-RAM Ready Register */

	out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));

	qe_iowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);

}



/*
@@ -509,7 +509,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware) 
	 * If the microcode calls for it, split the I-RAM.

	 */

	if (!firmware->split)

		setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);

		qe_setbits_be16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);



	if (firmware->soc.model)

		printk(KERN_INFO
@@ -543,11 +543,13 @@ int qe_upload_firmware(const struct qe_firmware *firmware) 
			u32 trap = be32_to_cpu(ucode->traps[j]);



			if (trap)

				out_be32(&qe_immr->rsp[i].tibcr[j], trap);

				qe_iowrite32be(trap,

					       &qe_immr->rsp[i].tibcr[j]);

		}



		/* Enable traps */

		out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));

		qe_iowrite32be(be32_to_cpu(ucode->eccr),

			       &qe_immr->rsp[i].eccr);

	}



	qe_firmware_uploaded = 1;

drivers/soc/fsl/qe/qe_ic.c

+3 −2
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
#include <linux/spinlock.h>

#include <asm/irq.h>

#include <asm/io.h>

#include <soc/fsl/qe/qe.h>

#include <soc/fsl/qe/qe_ic.h>



#include "qe_ic.h"
@@ -173,13 +174,13 @@ static struct qe_ic_info qe_ic_info[] = { 


static inline u32 qe_ic_read(__be32  __iomem *base, unsigned int reg)

{

	return in_be32(base + (reg >> 2));

	return qe_ioread32be(base + (reg >> 2));

}



static inline void qe_ic_write(__be32  __iomem *base, unsigned int reg,

			       u32 value)

{

	out_be32(base + (reg >> 2), value);

	qe_iowrite32be(value, base + (reg >> 2));

}



static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)

drivers/soc/fsl/qe/qe_io.c

+18 −22
Original line number Diff line number Diff line
@@ -57,16 +57,16 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir, 
	pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));



	/* Set open drain, if required */

	tmp_val = in_be32(&par_io->cpodr);

	tmp_val = qe_ioread32be(&par_io->cpodr);

	if (open_drain)

		out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);

		qe_iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);

	else

		out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);

		qe_iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);



	/* define direction */

	tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?

		in_be32(&par_io->cpdir2) :

		in_be32(&par_io->cpdir1);

		qe_ioread32be(&par_io->cpdir2) :

		qe_ioread32be(&par_io->cpdir1);



	/* get all bits mask for 2 bit per port */

	pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
@@ -78,34 +78,30 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir, 


	/* clear and set 2 bits mask */

	if (pin > (QE_PIO_PINS / 2) - 1) {

		out_be32(&par_io->cpdir2,

			 ~pin_mask2bits & tmp_val);

		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);

		tmp_val &= ~pin_mask2bits;

		out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);

		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);

	} else {

		out_be32(&par_io->cpdir1,

			 ~pin_mask2bits & tmp_val);

		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);

		tmp_val &= ~pin_mask2bits;

		out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);

		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);

	}

	/* define pin assignment */

	tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?

		in_be32(&par_io->cppar2) :

		in_be32(&par_io->cppar1);

		qe_ioread32be(&par_io->cppar2) :

		qe_ioread32be(&par_io->cppar1);



	new_mask2bits = (u32) (assignment << (QE_PIO_PINS -

			(pin % (QE_PIO_PINS / 2) + 1) * 2));

	/* clear and set 2 bits mask */

	if (pin > (QE_PIO_PINS / 2) - 1) {

		out_be32(&par_io->cppar2,

			 ~pin_mask2bits & tmp_val);

		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);

		tmp_val &= ~pin_mask2bits;

		out_be32(&par_io->cppar2, new_mask2bits | tmp_val);

		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);

	} else {

		out_be32(&par_io->cppar1,

			 ~pin_mask2bits & tmp_val);

		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);

		tmp_val &= ~pin_mask2bits;

		out_be32(&par_io->cppar1, new_mask2bits | tmp_val);

		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);

	}

}

EXPORT_SYMBOL(__par_io_config_pin);
@@ -133,12 +129,12 @@ int par_io_data_set(u8 port, u8 pin, u8 val) 
	/* calculate pin location */

	pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));



	tmp_val = in_be32(&par_io[port].cpdata);

	tmp_val = qe_ioread32be(&par_io[port].cpdata);



	if (val == 0)		/* clear */

		out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);

		qe_iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);

	else			/* set */

		out_be32(&par_io[port].cpdata, pin_mask | tmp_val);

		qe_iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);



	return 0;

}

drivers/soc/fsl/qe/qe_tdm.c

+4 −4
Original line number Diff line number Diff line
@@ -169,9 +169,9 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info) 
				    &siram[siram_entry_id * 32 + 0x200 +  i]);

	}



	setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],

	qe_setbits_be16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],

			SIR_LAST);

	setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],

	qe_setbits_be16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],

			SIR_LAST);



	/* Set SIxMR register */