Commit 77f36b27 authored by Zeyu Fan's avatar Zeyu Fan Committed by Alex Deucher
Browse files

drm/amd/display: Fix logic that causes segfault on DP display. 



Signed-off-by: default avatarZeyu Fan <Zeyu.Fan@amd.com>
Acked-by: default avatarJordan Lazare <Jordan.Lazare@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b3c64dff

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

+12 −10
Original line number Diff line number Diff line
@@ -852,17 +852,19 @@ static bool dce110_program_pix_clk( 
		 * during PLL Reset, but they do not have effect

		 * until SS_EN is asserted.*/

		if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL

			&& pix_clk_params->flags.ENABLE_SS && !dc_is_dp_signal(

							pix_clk_params->signal_type)) {

				&& !dc_is_dp_signal(pix_clk_params->signal_type)) {



			if (pix_clk_params->flags.ENABLE_SS)

				if (!enable_spread_spectrum(clk_src,

								pix_clk_params->signal_type,

								pll_settings))

					return false;

		}



			/* Resync deep color DTO */

			dce110_program_pixel_clk_resync(clk_src,

						pix_clk_params->signal_type,

						pix_clk_params->color_depth);

		}



		break;

	case DCE_VERSION_11_2: