Commit 78842457 authored by David M Nieto's avatar David M Nieto Committed by Alex Deucher
Browse files

drm/amdgpu/pm: display vcn pp dpm (v4) 



Enable displaying DPM levels for VCN clocks
in swsmu supported ASICs

v2: removed set functions for navi, renoir
v3: removed set function from arcturus
v4: added missing defines in drm_table and remove
 uneeded goto label in navi10_ppt.c

Signed-off-by: default avatarDavid M Nieto <david.nieto@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 61e2d322

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

+4 −0
Original line number Diff line number Diff line
@@ -245,6 +245,8 @@ struct pp_smu_funcs_nv { 
#define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8

#define PP_SMU_NUM_FCLK_DPM_LEVELS    4

#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  4

#define PP_SMU_NUM_DCLK_DPM_LEVELS    8

#define PP_SMU_NUM_VCLK_DPM_LEVELS    8



struct dpm_clock {

  uint32_t  Freq;    // In MHz
@@ -258,6 +260,8 @@ struct dpm_clocks { 
	struct dpm_clock SocClocks[PP_SMU_NUM_SOCCLK_DPM_LEVELS];

	struct dpm_clock FClocks[PP_SMU_NUM_FCLK_DPM_LEVELS];

	struct dpm_clock MemClocks[PP_SMU_NUM_MEMCLK_DPM_LEVELS];

	struct dpm_clock VClocks[PP_SMU_NUM_VCLK_DPM_LEVELS];

	struct dpm_clock DClocks[PP_SMU_NUM_DCLK_DPM_LEVELS];

};

drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

+46 −0
Original line number Diff line number Diff line
@@ -822,6 +822,52 @@ static int arcturus_print_clk_levels(struct smu_context *smu, 
				now) ? "*" : ""));

		break;



	case SMU_VCLK:

		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);

		if (ret) {

			dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");

			return ret;

		}



		single_dpm_table = &(dpm_context->dpm_tables.vclk_table);

		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);

		if (ret) {

			dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");

			return ret;

		}



		for (i = 0; i < single_dpm_table->count; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

				i, single_dpm_table->dpm_levels[i].value,

				(clocks.num_levels == 1) ? "*" :

				(arcturus_freqs_in_same_level(

				clocks.data[i].clocks_in_khz / 1000,

				now) ? "*" : ""));

		break;



	case SMU_DCLK:

		ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);

		if (ret) {

			dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");

			return ret;

		}



		single_dpm_table = &(dpm_context->dpm_tables.dclk_table);

		ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);

		if (ret) {

			dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");

			return ret;

		}



		for (i = 0; i < single_dpm_table->count; i++)

			size += sprintf(buf + size, "%d: %uMhz %s\n",

				i, single_dpm_table->dpm_levels[i].value,

				(clocks.num_levels == 1) ? "*" :

				(arcturus_freqs_in_same_level(

				clocks.data[i].clocks_in_khz / 1000,

				now) ? "*" : ""));

		break;



	case SMU_PCIE:

		gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);

		lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);

drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c

+2 −8
Original line number Diff line number Diff line
@@ -1273,6 +1273,8 @@ static int navi10_print_clk_levels(struct smu_context *smu, 
	case SMU_MCLK:

	case SMU_UCLK:

	case SMU_FCLK:

	case SMU_VCLK:

	case SMU_DCLK:

	case SMU_DCEFCLK:

		ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);

		if (ret)
@@ -2694,8 +2696,6 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, 
	*table = (void *)gpu_metrics;



	return sizeof(struct gpu_metrics_v1_3);

out:

	return ret;

}



static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
@@ -2771,8 +2771,6 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, 
	*table = (void *)gpu_metrics;



	return sizeof(struct gpu_metrics_v1_3);

out:

	return ret;

}



static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
@@ -2851,8 +2849,6 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, 
	*table = (void *)gpu_metrics;



	return sizeof(struct gpu_metrics_v1_3);

out:

	return ret;

}



static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
@@ -2933,8 +2929,6 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, 
	*table = (void *)gpu_metrics;



	return sizeof(struct gpu_metrics_v1_3);

out:

	return ret;

}



static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+4 −0
Original line number Diff line number Diff line
@@ -987,6 +987,10 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, 
	case SMU_MCLK:

	case SMU_UCLK:

	case SMU_FCLK:

	case SMU_VCLK:

	case SMU_VCLK1:

	case SMU_DCLK:

	case SMU_DCLK1:

	case SMU_DCEFCLK:

		ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);

		if (ret)

drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c

+33 −0
Original line number Diff line number Diff line
@@ -109,6 +109,8 @@ static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = { 
	CLK_MAP(SOCCLK, CLOCK_SOCCLK),

	CLK_MAP(UCLK, CLOCK_FCLK),

	CLK_MAP(MCLK, CLOCK_FCLK),

	CLK_MAP(VCLK, CLOCK_VCLK),

	CLK_MAP(DCLK, CLOCK_DCLK),

};



static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
@@ -202,6 +204,17 @@ static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type 
			return -EINVAL;

		*freq = clk_table->FClocks[dpm_level].Freq;

		break;

	case SMU_VCLK:

		if (dpm_level >= NUM_VCN_DPM_LEVELS)

			return -EINVAL;

		*freq = clk_table->VClocks[dpm_level].Freq;

		break;

	case SMU_DCLK:

		if (dpm_level >= NUM_VCN_DPM_LEVELS)

			return -EINVAL;

		*freq = clk_table->DClocks[dpm_level].Freq;

		break;



	default:

		return -EINVAL;

	}
@@ -532,6 +545,14 @@ static int renoir_print_clk_levels(struct smu_context *smu, 
		count = NUM_FCLK_DPM_LEVELS;

		cur_value = metrics.ClockFrequency[CLOCK_FCLK];

		break;

	case SMU_VCLK:

		count = NUM_VCN_DPM_LEVELS;

		cur_value = metrics.ClockFrequency[CLOCK_VCLK];

		break;

	case SMU_DCLK:

		count = NUM_VCN_DPM_LEVELS;

		cur_value = metrics.ClockFrequency[CLOCK_DCLK];

		break;

	default:

		break;

	}
@@ -543,6 +564,8 @@ static int renoir_print_clk_levels(struct smu_context *smu, 
	case SMU_MCLK:

	case SMU_DCEFCLK:

	case SMU_FCLK:

	case SMU_VCLK:

	case SMU_DCLK:

		for (i = 0; i < count; i++) {

			ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value);

			if (ret)
@@ -730,6 +753,16 @@ static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks 
		clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;

	}



	for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {

		clock_table->VClocks[i].Freq = table->VClocks[i].Freq;

		clock_table->VClocks[i].Vol = table->VClocks[i].Vol;

	}



	for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {

		clock_table->DClocks[i].Freq = table->DClocks[i].Freq;

		clock_table->DClocks[i].Vol = table->DClocks[i].Vol;

	}



	return 0;

}