Commit 790bef48 authored by YiPeng Chai's avatar YiPeng Chai Committed by Alex Deucher
Browse files

drm/amdgpu: Add gfx cp ecc error irq handling on gfx v11_0_3 



V2:
  Optimize gfx_v11_0_set_cp_ecc_error_state function.

V3:
  Define macro constant for me pipe instance address interval.

V5:
  Register and handle gfx cp ecc error irq on gfx v11_0_3.

V6:
  Remove invalid intermediate function call.

Signed-off-by: default avatarYiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ae6f2db4

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+47 −0
Original line number Diff line number Diff line
@@ -1301,6 +1301,13 @@ static int gfx_v11_0_sw_init(void *handle) 
	if (r)

		return r;



	/* ECC error */

	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,

				  GFX_11_0_0__SRCID__CP_ECC_ERROR,

				  &adev->gfx.cp_ecc_error_irq);

	if (r)

		return r;



	/* FED error */

	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,

				  GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT,
@@ -4392,6 +4399,7 @@ static int gfx_v11_0_hw_fini(void *handle) 
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	int r;



	amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);

	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
@@ -5823,6 +5831,36 @@ static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev 
	}

}



#define CP_ME1_PIPE_INST_ADDR_INTERVAL  0x1

#define SET_ECC_ME_PIPE_STATE(reg_addr, state) \

	do { \

		uint32_t tmp = RREG32_SOC15_IP(GC, reg_addr); \

		tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, state); \

		WREG32_SOC15_IP(GC, reg_addr, tmp); \

	} while (0)



static int gfx_v11_0_set_cp_ecc_error_state(struct amdgpu_device *adev,

							struct amdgpu_irq_src *source,

							unsigned type,

							enum amdgpu_interrupt_state state)

{

	uint32_t ecc_irq_state = 0;

	uint32_t pipe0_int_cntl_addr = 0;

	int i = 0;



	ecc_irq_state = (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0;



	pipe0_int_cntl_addr = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);



	WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, ecc_irq_state);



	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++)

		SET_ECC_ME_PIPE_STATE(pipe0_int_cntl_addr + i * CP_ME1_PIPE_INST_ADDR_INTERVAL,

					ecc_irq_state);



	return 0;

}



static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,

					    struct amdgpu_irq_src *src,

					    unsigned type,
@@ -6239,6 +6277,11 @@ static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = { 
	.process = gfx_v11_0_priv_inst_irq,

};



static const struct amdgpu_irq_src_funcs gfx_v11_0_cp_ecc_error_irq_funcs = {

	.set = gfx_v11_0_set_cp_ecc_error_state,

	.process = amdgpu_gfx_cp_ecc_error_irq,

};



static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = {

	.process = gfx_v11_0_rlc_gc_fed_irq,

};
@@ -6254,8 +6297,12 @@ static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev) 
	adev->gfx.priv_inst_irq.num_types = 1;

	adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;



	adev->gfx.cp_ecc_error_irq.num_types = 1; /* CP ECC error */

	adev->gfx.cp_ecc_error_irq.funcs = &gfx_v11_0_cp_ecc_error_irq_funcs;



	adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */

	adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;



}



static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)