Commit 792ba321 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Greg Kroah-Hartman
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bus: mhi: Cleanup the register definitions used in headers 



Cleanup includes:

1. Using the GENMASK macro for masks
2. Removing brackets for single values
3. Using lowercase for hex values
4. Using two digits for hex values where applicable
5. Aligning the defines on same column

Reviewed-by: default avatarHemant Kumar <hemantk@codeaurora.org>
Reviewed-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20220301160308.107452-8-manivannan.sadhasivam@linaro.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent ba1d2b86

drivers/bus/mhi/host/internal.h

+199 −214
Original line number Original line Diff line number Diff line
@@ -12,130 +12,112 @@ 




extern struct bus_type mhi_bus_type;

extern struct bus_type mhi_bus_type;





#define MHIREGLEN (0x0)

/* MHI registers */



#define MHIREGLEN					0x00

#define MHIVER (0x8)

#define MHIVER						0x08



#define MHICFG						0x10

#define MHICFG (0x10)

#define CHDBOFF						0x18

#define MHICFG_NHWER_MASK (GENMASK(31, 24))

#define ERDBOFF						0x20

#define MHICFG_NER_MASK (GENMASK(23, 16))

#define BHIOFF						0x28

#define MHICFG_NHWCH_MASK (GENMASK(15, 8))

#define BHIEOFF						0x2c

#define MHICFG_NCH_MASK (GENMASK(7, 0))

#define DEBUGOFF					0x30



#define MHICTRL						0x38

#define CHDBOFF (0x18)

#define MHISTATUS					0x48



#define CCABAP_LOWER					0x58

#define ERDBOFF (0x20)

#define CCABAP_HIGHER					0x5c



#define ECABAP_LOWER					0x60

#define BHIOFF (0x28)

#define ECABAP_HIGHER					0x64



#define CRCBAP_LOWER					0x68

#define BHIEOFF (0x2C)

#define CRCBAP_HIGHER					0x6c



#define CRDB_LOWER					0x70

#define DEBUGOFF (0x30)

#define CRDB_HIGHER					0x74



#define MHICTRLBASE_LOWER				0x80

#define MHICTRL (0x38)

#define MHICTRLBASE_HIGHER				0x84

#define MHICTRL_MHISTATE_MASK (GENMASK(15, 8))

#define MHICTRLLIMIT_LOWER				0x88

#define MHICTRL_RESET_MASK (BIT(1))

#define MHICTRLLIMIT_HIGHER				0x8c



#define MHIDATABASE_LOWER				0x98

#define MHISTATUS (0x48)

#define MHIDATABASE_HIGHER				0x9c

#define MHISTATUS_MHISTATE_MASK (GENMASK(15, 8))

#define MHIDATALIMIT_LOWER				0xa0

#define MHISTATUS_SYSERR_MASK (BIT(2))

#define MHIDATALIMIT_HIGHER				0xa4

#define MHISTATUS_READY_MASK (BIT(0))



#define CCABAP_LOWER (0x58)



#define CCABAP_HIGHER (0x5C)



#define ECABAP_LOWER (0x60)



#define ECABAP_HIGHER (0x64)



#define CRCBAP_LOWER (0x68)



#define CRCBAP_HIGHER (0x6C)



#define CRDB_LOWER (0x70)



#define CRDB_HIGHER (0x74)



#define MHICTRLBASE_LOWER (0x80)



#define MHICTRLBASE_HIGHER (0x84)



#define MHICTRLLIMIT_LOWER (0x88)



#define MHICTRLLIMIT_HIGHER (0x8C)



#define MHIDATABASE_LOWER (0x98)



#define MHIDATABASE_HIGHER (0x9C)



#define MHIDATALIMIT_LOWER (0xA0)



#define MHIDATALIMIT_HIGHER (0xA4)





/* Host request register */

/* Host request register */

#define MHI_SOC_RESET_REQ_OFFSET (0xB0)

#define MHI_SOC_RESET_REQ_OFFSET			0xb0

#define MHI_SOC_RESET_REQ				BIT(0)

#define MHI_SOC_RESET_REQ				BIT(0)





/* MHI BHI offfsets */

/* MHI register bits */

#define BHI_BHIVERSION_MINOR (0x00)

#define MHICFG_NHWER_MASK				GENMASK(31, 24)

#define BHI_BHIVERSION_MAJOR (0x04)

#define MHICFG_NER_MASK					GENMASK(23, 16)

#define BHI_IMGADDR_LOW (0x08)

#define MHICFG_NHWCH_MASK				GENMASK(15, 8)

#define BHI_IMGADDR_HIGH (0x0C)

#define MHICFG_NCH_MASK					GENMASK(7, 0)

#define BHI_IMGSIZE (0x10)

#define MHICTRL_MHISTATE_MASK				GENMASK(15, 8)

#define BHI_RSVD1 (0x14)

#define MHICTRL_RESET_MASK				BIT(1)

#define BHI_IMGTXDB (0x18)

#define MHISTATUS_MHISTATE_MASK				GENMASK(15, 8)

#define BHI_TXDB_SEQNUM_BMSK (GENMASK(29, 0))

#define MHISTATUS_SYSERR_MASK				BIT(2)

#define BHI_RSVD2 (0x1C)

#define MHISTATUS_READY_MASK				BIT(0)

#define BHI_INTVEC (0x20)



#define BHI_RSVD3 (0x24)

/* MHI BHI registers */

#define BHI_EXECENV (0x28)

#define BHI_BHIVERSION_MINOR				0x00

#define BHI_STATUS (0x2C)

#define BHI_BHIVERSION_MAJOR				0x04

#define BHI_ERRCODE (0x30)

#define BHI_IMGADDR_LOW					0x08

#define BHI_ERRDBG1 (0x34)

#define BHI_IMGADDR_HIGH				0x0c

#define BHI_ERRDBG2 (0x38)

#define BHI_IMGSIZE					0x10

#define BHI_ERRDBG3 (0x3C)

#define BHI_RSVD1					0x14

#define BHI_SERIALNU (0x40)

#define BHI_IMGTXDB					0x18

#define BHI_SBLANTIROLLVER (0x44)

#define BHI_RSVD2					0x1c

#define BHI_NUMSEG (0x48)

#define BHI_INTVEC					0x20

#define BHI_MSMHWID(n) (0x4C + (0x4 * (n)))

#define BHI_RSVD3					0x24

#define BHI_EXECENV					0x28

#define BHI_STATUS					0x2c

#define BHI_ERRCODE					0x30

#define BHI_ERRDBG1					0x34

#define BHI_ERRDBG2					0x38

#define BHI_ERRDBG3					0x3c

#define BHI_SERIALNU					0x40

#define BHI_SBLANTIROLLVER				0x44

#define BHI_NUMSEG					0x48

#define BHI_MSMHWID(n)					(0x4c + (0x4 * (n)))

#define BHI_OEMPKHASH(n)				(0x64 + (0x4 * (n)))

#define BHI_OEMPKHASH(n)				(0x64 + (0x4 * (n)))

#define BHI_RSVD5 (0xC4)

#define BHI_RSVD5					0xc4

#define BHI_STATUS_MASK (GENMASK(31, 30))



#define BHI_STATUS_ERROR (3)

/* BHI register bits */

#define BHI_STATUS_SUCCESS (2)

#define BHI_TXDB_SEQNUM_BMSK				GENMASK(29, 0)

#define BHI_STATUS_RESET (0)

#define BHI_STATUS_MASK					GENMASK(31, 30)



#define BHI_STATUS_ERROR				0x03

/* MHI BHIE offsets */

#define BHI_STATUS_SUCCESS				0x02

#define BHIE_MSMSOCID_OFFS (0x0000)

#define BHI_STATUS_RESET				0x00

#define BHIE_TXVECADDR_LOW_OFFS (0x002C)



#define BHIE_TXVECADDR_HIGH_OFFS (0x0030)

/* MHI BHIE registers */

#define BHIE_TXVECSIZE_OFFS (0x0034)

#define BHIE_MSMSOCID_OFFS				0x00

#define BHIE_TXVECDB_OFFS (0x003C)

#define BHIE_TXVECADDR_LOW_OFFS				0x2c

#define BHIE_TXVECDB_SEQNUM_BMSK (GENMASK(29, 0))

#define BHIE_TXVECADDR_HIGH_OFFS			0x30

#define BHIE_TXVECSTATUS_OFFS (0x0044)

#define BHIE_TXVECSIZE_OFFS				0x34

#define BHIE_TXVECSTATUS_SEQNUM_BMSK (GENMASK(29, 0))

#define BHIE_TXVECDB_OFFS				0x3c

#define BHIE_TXVECSTATUS_STATUS_BMSK (GENMASK(31, 30))

#define BHIE_TXVECSTATUS_OFFS				0x44

#define BHIE_TXVECSTATUS_STATUS_RESET (0x00)

#define BHIE_RXVECADDR_LOW_OFFS				0x60

#define BHIE_TXVECSTATUS_STATUS_XFER_COMPL (0x02)

#define BHIE_RXVECADDR_HIGH_OFFS			0x64

#define BHIE_TXVECSTATUS_STATUS_ERROR (0x03)

#define BHIE_RXVECSIZE_OFFS				0x68

#define BHIE_RXVECADDR_LOW_OFFS (0x0060)

#define BHIE_RXVECDB_OFFS				0x70

#define BHIE_RXVECADDR_HIGH_OFFS (0x0064)

#define BHIE_RXVECSTATUS_OFFS				0x78

#define BHIE_RXVECSIZE_OFFS (0x0068)



#define BHIE_RXVECDB_OFFS (0x0070)

/* BHIE register bits */

#define BHIE_RXVECDB_SEQNUM_BMSK (GENMASK(29, 0))

#define BHIE_TXVECDB_SEQNUM_BMSK			GENMASK(29, 0)

#define BHIE_RXVECSTATUS_OFFS (0x0078)

#define BHIE_TXVECSTATUS_SEQNUM_BMSK			GENMASK(29, 0)

#define BHIE_RXVECSTATUS_SEQNUM_BMSK (GENMASK(29, 0))

#define BHIE_TXVECSTATUS_STATUS_BMSK			GENMASK(31, 30)

#define BHIE_RXVECSTATUS_STATUS_BMSK (GENMASK(31, 30))

#define BHIE_TXVECSTATUS_STATUS_RESET			0x00

#define BHIE_RXVECSTATUS_STATUS_RESET (0x00)

#define BHIE_TXVECSTATUS_STATUS_XFER_COMPL		0x02

#define BHIE_RXVECSTATUS_STATUS_XFER_COMPL (0x02)

#define BHIE_TXVECSTATUS_STATUS_ERROR			0x03

#define BHIE_RXVECSTATUS_STATUS_ERROR (0x03)

#define BHIE_RXVECDB_SEQNUM_BMSK			GENMASK(29, 0)



#define BHIE_RXVECSTATUS_SEQNUM_BMSK			GENMASK(29, 0)

#define SOC_HW_VERSION_OFFS (0x224)

#define BHIE_RXVECSTATUS_STATUS_BMSK			GENMASK(31, 30)

#define SOC_HW_VERSION_FAM_NUM_BMSK (GENMASK(31, 28))

#define BHIE_RXVECSTATUS_STATUS_RESET			0x00

#define SOC_HW_VERSION_DEV_NUM_BMSK (GENMASK(27, 16))

#define BHIE_RXVECSTATUS_STATUS_XFER_COMPL		0x02

#define SOC_HW_VERSION_MAJOR_VER_BMSK (GENMASK(15, 8))

#define BHIE_RXVECSTATUS_STATUS_ERROR			0x03

#define SOC_HW_VERSION_MINOR_VER_BMSK (GENMASK(7, 0))



#define SOC_HW_VERSION_OFFS				0x224

#define SOC_HW_VERSION_FAM_NUM_BMSK			GENMASK(31, 28)

#define SOC_HW_VERSION_DEV_NUM_BMSK			GENMASK(27, 16)

#define SOC_HW_VERSION_MAJOR_VER_BMSK			GENMASK(15, 8)

#define SOC_HW_VERSION_MINOR_VER_BMSK			GENMASK(7, 0)





#define EV_CTX_RESERVED_MASK				GENMASK(7, 0)

#define EV_CTX_RESERVED_MASK				GENMASK(7, 0)

#define EV_CTX_INTMODC_MASK				GENMASK(15, 8)

#define EV_CTX_INTMODC_MASK				GENMASK(15, 8)
@@ -204,67 +186,71 @@ enum mhi_cmd_type { 
};

};





/* No operation command */

/* No operation command */

#define MHI_TRE_CMD_NOOP_PTR (0)

#define MHI_TRE_CMD_NOOP_PTR		0

#define MHI_TRE_CMD_NOOP_DWORD0 (0)

#define MHI_TRE_CMD_NOOP_DWORD0		0

#define MHI_TRE_CMD_NOOP_DWORD1 (cpu_to_le32(FIELD_PREP(GENMASK(23, 16), MHI_CMD_NOP)))

#define MHI_TRE_CMD_NOOP_DWORD1		cpu_to_le32(FIELD_PREP(GENMASK(23, 16), MHI_CMD_NOP))





/* Channel reset command */

/* Channel reset command */

#define MHI_TRE_CMD_RESET_PTR (0)

#define MHI_TRE_CMD_RESET_PTR		0

#define MHI_TRE_CMD_RESET_DWORD0 (0)

#define MHI_TRE_CMD_RESET_DWORD0	0

#define MHI_TRE_CMD_RESET_DWORD1(chid) (cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid)) | \

#define MHI_TRE_CMD_RESET_DWORD1(chid)	cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \

					FIELD_PREP(GENMASK(23, 16), MHI_CMD_RESET_CHAN))

						    FIELD_PREP(GENMASK(23, 16),         \

							       MHI_CMD_RESET_CHAN))





/* Channel stop command */

/* Channel stop command */

#define MHI_TRE_CMD_STOP_PTR (0)

#define MHI_TRE_CMD_STOP_PTR		0

#define MHI_TRE_CMD_STOP_DWORD0 (0)

#define MHI_TRE_CMD_STOP_DWORD0		0

#define MHI_TRE_CMD_STOP_DWORD1(chid) (cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid)) | \

#define MHI_TRE_CMD_STOP_DWORD1(chid)	cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \

					FIELD_PREP(GENMASK(23, 16), MHI_CMD_STOP_CHAN))

						    FIELD_PREP(GENMASK(23, 16),         \

							       MHI_CMD_STOP_CHAN))





/* Channel start command */

/* Channel start command */

#define MHI_TRE_CMD_START_PTR (0)

#define MHI_TRE_CMD_START_PTR		0

#define MHI_TRE_CMD_START_DWORD0 (0)

#define MHI_TRE_CMD_START_DWORD0	0

#define MHI_TRE_CMD_START_DWORD1(chid) (cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid)) | \

#define MHI_TRE_CMD_START_DWORD1(chid)	cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \

					FIELD_PREP(GENMASK(23, 16), MHI_CMD_START_CHAN))

						    FIELD_PREP(GENMASK(23, 16),         \

							       MHI_CMD_START_CHAN))





#define MHI_TRE_GET_DWORD(tre, word) (le32_to_cpu((tre)->dword[(word)]))

#define MHI_TRE_GET_DWORD(tre, word)	le32_to_cpu((tre)->dword[(word)])

#define MHI_TRE_GET_CMD_CHID(tre) (FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1))))

#define MHI_TRE_GET_CMD_CHID(tre)	FIELD_GET(GENMASK(31, 24), MHI_TRE_GET_DWORD(tre, 1))

#define MHI_TRE_GET_CMD_TYPE(tre) (FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 1))))

#define MHI_TRE_GET_CMD_TYPE(tre)	FIELD_GET(GENMASK(23, 16), MHI_TRE_GET_DWORD(tre, 1))





/* Event descriptor macros */

/* Event descriptor macros */

#define MHI_TRE_EV_PTR(ptr) (cpu_to_le64(ptr))

#define MHI_TRE_EV_PTR(ptr)		cpu_to_le64(ptr)

#define MHI_TRE_EV_DWORD0(code, len) (cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code) | \

#define MHI_TRE_EV_DWORD0(code, len)	cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code | \

						    FIELD_PREP(GENMASK(15, 0), len)))

						    FIELD_PREP(GENMASK(15, 0), len)))

#define MHI_TRE_EV_DWORD1(chid, type) (cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \

#define MHI_TRE_EV_DWORD1(chid, type)	cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid | \

						    FIELD_PREP(GENMASK(23, 16), type)))

						    FIELD_PREP(GENMASK(23, 16), type)))

#define MHI_TRE_GET_EV_PTR(tre) (le64_to_cpu((tre)->ptr))

#define MHI_TRE_GET_EV_PTR(tre)		le64_to_cpu((tre)->ptr)

#define MHI_TRE_GET_EV_CODE(tre) (FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0))))

#define MHI_TRE_GET_EV_CODE(tre)	FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))

#define MHI_TRE_GET_EV_LEN(tre) (FIELD_GET(GENMASK(15, 0), (MHI_TRE_GET_DWORD(tre, 0))))

#define MHI_TRE_GET_EV_LEN(tre)		FIELD_GET(GENMASK(15, 0), (MHI_TRE_GET_DWORD(tre, 0)))

#define MHI_TRE_GET_EV_CHID(tre) (FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1))))

#define MHI_TRE_GET_EV_CHID(tre)	FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))

#define MHI_TRE_GET_EV_TYPE(tre) (FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 1))))

#define MHI_TRE_GET_EV_TYPE(tre)	FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 1)))

#define MHI_TRE_GET_EV_STATE(tre) (FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0))))

#define MHI_TRE_GET_EV_STATE(tre)	FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))

#define MHI_TRE_GET_EV_EXECENV(tre) (FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0))))

#define MHI_TRE_GET_EV_EXECENV(tre)	FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 0)))

#define MHI_TRE_GET_EV_SEQ(tre)		MHI_TRE_GET_DWORD(tre, 0)

#define MHI_TRE_GET_EV_SEQ(tre)		MHI_TRE_GET_DWORD(tre, 0)

#define MHI_TRE_GET_EV_TIME(tre) (MHI_TRE_GET_EV_PTR(tre))

#define MHI_TRE_GET_EV_TIME(tre)	MHI_TRE_GET_EV_PTR(tre)

#define MHI_TRE_GET_EV_COOKIE(tre)	lower_32_bits(MHI_TRE_GET_EV_PTR(tre))

#define MHI_TRE_GET_EV_COOKIE(tre)	lower_32_bits(MHI_TRE_GET_EV_PTR(tre))

#define MHI_TRE_GET_EV_VEID(tre) (FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 0))))

#define MHI_TRE_GET_EV_VEID(tre)	FIELD_GET(GENMASK(23, 16), (MHI_TRE_GET_DWORD(tre, 0)))

#define MHI_TRE_GET_EV_LINKSPEED(tre) (FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1))))

#define MHI_TRE_GET_EV_LINKSPEED(tre)	FIELD_GET(GENMASK(31, 24), (MHI_TRE_GET_DWORD(tre, 1)))

#define MHI_TRE_GET_EV_LINKWIDTH(tre) (FIELD_GET(GENMASK(7, 0), (MHI_TRE_GET_DWORD(tre, 0))))

#define MHI_TRE_GET_EV_LINKWIDTH(tre)	FIELD_GET(GENMASK(7, 0), (MHI_TRE_GET_DWORD(tre, 0)))





/* Transfer descriptor macros */

/* Transfer descriptor macros */

#define MHI_TRE_DATA_PTR(ptr) (cpu_to_le64(ptr))

#define MHI_TRE_DATA_PTR(ptr)		cpu_to_le64(ptr)

#define MHI_TRE_DATA_DWORD0(len) (cpu_to_le32(FIELD_PREP(GENMASK(15, 0), len)))

#define MHI_TRE_DATA_DWORD0(len)	cpu_to_le32(FIELD_PREP(GENMASK(15, 0), len))

#define MHI_TRE_TYPE_TRANSFER		2

#define MHI_TRE_TYPE_TRANSFER		2

#define MHI_TRE_DATA_DWORD1(bei, ieot, ieob, chain) (cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \

#define MHI_TRE_DATA_DWORD1(bei, ieot, ieob, chain) cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \

								MHI_TRE_TYPE_TRANSFER) |    \

								MHI_TRE_TYPE_TRANSFER) |    \

								FIELD_PREP(BIT(10), bei) |  \

								FIELD_PREP(BIT(10), bei) |  \

								FIELD_PREP(BIT(9), ieot) |  \

								FIELD_PREP(BIT(9), ieot) |  \

								FIELD_PREP(BIT(8), ieob) |  \

								FIELD_PREP(BIT(8), ieob) |  \

							FIELD_PREP(BIT(0), chain)))

								FIELD_PREP(BIT(0), chain))





/* RSC transfer descriptor macros */

/* RSC transfer descriptor macros */

#define MHI_RSCTRE_DATA_PTR(ptr, len) (cpu_to_le64(FIELD_PREP(GENMASK(64, 48), len) | ptr))

#define MHI_RSCTRE_DATA_PTR(ptr, len)	cpu_to_le64(FIELD_PREP(GENMASK(64, 48), len) | ptr)

#define MHI_RSCTRE_DATA_DWORD0(cookie) (cpu_to_le32(cookie))

#define MHI_RSCTRE_DATA_DWORD0(cookie)	cpu_to_le32(cookie)

#define MHI_RSCTRE_DATA_DWORD1 (cpu_to_le32(FIELD_PREP(GENMASK(23, 16), MHI_PKT_TYPE_COALESCING)

#define MHI_RSCTRE_DATA_DWORD1		cpu_to_le32(FIELD_PREP(GENMASK(23, 16), \

							       MHI_PKT_TYPE_COALESCING))





enum mhi_pkt_type {

enum mhi_pkt_type {

	MHI_PKT_TYPE_INVALID = 0x0,

	MHI_PKT_TYPE_INVALID = 0x0,
@@ -390,8 +376,7 @@ enum mhi_pm_state { 
						MHI_PM_SHUTDOWN_PROCESS | MHI_PM_FW_DL_ERR)))

						MHI_PM_SHUTDOWN_PROCESS | MHI_PM_FW_DL_ERR)))

#define MHI_PM_IN_ERROR_STATE(pm_state)			(pm_state >= MHI_PM_FW_DL_ERR)

#define MHI_PM_IN_ERROR_STATE(pm_state)			(pm_state >= MHI_PM_FW_DL_ERR)

#define MHI_PM_IN_FATAL_STATE(pm_state)			(pm_state == MHI_PM_LD_ERR_FATAL_DETECT)

#define MHI_PM_IN_FATAL_STATE(pm_state)			(pm_state == MHI_PM_LD_ERR_FATAL_DETECT)

#define MHI_DB_ACCESS_VALID(mhi_cntrl) (mhi_cntrl->pm_state & \

#define MHI_DB_ACCESS_VALID(mhi_cntrl)			(mhi_cntrl->pm_state & mhi_cntrl->db_access)

					mhi_cntrl->db_access)

#define MHI_WAKE_DB_CLEAR_VALID(pm_state)		(pm_state & (MHI_PM_M0 | \

#define MHI_WAKE_DB_CLEAR_VALID(pm_state)		(pm_state & (MHI_PM_M0 | \

							MHI_PM_M2 | MHI_PM_M3_EXIT))

							MHI_PM_M2 | MHI_PM_M3_EXIT))

#define MHI_WAKE_DB_SET_VALID(pm_state)			(pm_state & MHI_PM_M2)

#define MHI_WAKE_DB_SET_VALID(pm_state)			(pm_state & MHI_PM_M2)