Loading drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h +1 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,7 @@ void nvkm_mc_reset(struct nvkm_mc *, enum nvkm_devidx); void nvkm_mc_unk260(struct nvkm_mc *, u32 data); int nv04_mc_new(struct nvkm_device *, int, struct nvkm_mc **); int nv17_mc_new(struct nvkm_device *, int, struct nvkm_mc **); int nv44_mc_new(struct nvkm_device *, int, struct nvkm_mc **); int nv50_mc_new(struct nvkm_device *, int, struct nvkm_mc **); int g84_mc_new(struct nvkm_device *, int, struct nvkm_mc **); Loading drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +20 −20 Original line number Diff line number Diff line Loading @@ -190,7 +190,7 @@ nv17_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -212,7 +212,7 @@ nv18_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading Loading @@ -256,7 +256,7 @@ nv1f_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -278,7 +278,7 @@ nv20_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -300,7 +300,7 @@ nv25_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -322,7 +322,7 @@ nv28_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -344,7 +344,7 @@ nv2a_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -366,7 +366,7 @@ nv30_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -388,7 +388,7 @@ nv31_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -411,7 +411,7 @@ nv34_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -434,7 +434,7 @@ nv35_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -456,7 +456,7 @@ nv36_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -479,7 +479,7 @@ nv40_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading @@ -505,7 +505,7 @@ nv41_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading @@ -531,7 +531,7 @@ nv42_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading @@ -557,7 +557,7 @@ nv43_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading Loading @@ -609,7 +609,7 @@ nv45_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading Loading @@ -661,7 +661,7 @@ nv47_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading @@ -687,7 +687,7 @@ nv49_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading Loading @@ -739,7 +739,7 @@ nv4b_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c +27 −0 Original line number Diff line number Diff line Loading @@ -30,3 +30,30 @@ nv17_mc_reset[] = { { 0x00000002, NVKM_ENGINE_MPEG }, {} }; const struct nvkm_mc_map nv17_mc_intr[] = { { 0x03010000, NVKM_ENGINE_DISP }, { 0x00001000, NVKM_ENGINE_GR }, { 0x00000100, NVKM_ENGINE_FIFO }, { 0x00000001, NVKM_ENGINE_MPEG }, { 0x10000000, NVKM_SUBDEV_BUS }, { 0x00100000, NVKM_SUBDEV_TIMER }, {} }; static const struct nvkm_mc_func nv17_mc = { .init = nv04_mc_init, .intr = nv17_mc_intr, .intr_unarm = nv04_mc_intr_unarm, .intr_rearm = nv04_mc_intr_rearm, .intr_mask = nv04_mc_intr_mask, .reset = nv17_mc_reset, }; int nv17_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) { return nvkm_mc_new_(&nv17_mc, device, index, pmc); } drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c +2 −1 Original line number Diff line number Diff line Loading @@ -40,10 +40,11 @@ nv44_mc_init(struct nvkm_mc *mc) static const struct nvkm_mc_func nv44_mc = { .init = nv44_mc_init, .intr = nv04_mc_intr, .intr = nv17_mc_intr, .intr_unarm = nv04_mc_intr_unarm, .intr_rearm = nv04_mc_intr_rearm, .intr_mask = nv04_mc_intr_mask, .reset = nv17_mc_reset, }; int Loading drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c +1 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,7 @@ nv50_mc = { .intr_unarm = nv04_mc_intr_unarm, .intr_rearm = nv04_mc_intr_rearm, .intr_mask = nv04_mc_intr_mask, .reset = nv17_mc_reset, }; int Loading Loading
drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h +1 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,7 @@ void nvkm_mc_reset(struct nvkm_mc *, enum nvkm_devidx); void nvkm_mc_unk260(struct nvkm_mc *, u32 data); int nv04_mc_new(struct nvkm_device *, int, struct nvkm_mc **); int nv17_mc_new(struct nvkm_device *, int, struct nvkm_mc **); int nv44_mc_new(struct nvkm_device *, int, struct nvkm_mc **); int nv50_mc_new(struct nvkm_device *, int, struct nvkm_mc **); int g84_mc_new(struct nvkm_device *, int, struct nvkm_mc **); Loading
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +20 −20 Original line number Diff line number Diff line Loading @@ -190,7 +190,7 @@ nv17_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -212,7 +212,7 @@ nv18_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading Loading @@ -256,7 +256,7 @@ nv1f_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -278,7 +278,7 @@ nv20_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -300,7 +300,7 @@ nv25_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -322,7 +322,7 @@ nv28_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -344,7 +344,7 @@ nv2a_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -366,7 +366,7 @@ nv30_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -388,7 +388,7 @@ nv31_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -411,7 +411,7 @@ nv34_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -434,7 +434,7 @@ nv35_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -456,7 +456,7 @@ nv36_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv04_pci_new, .timer = nv04_timer_new, Loading @@ -479,7 +479,7 @@ nv40_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading @@ -505,7 +505,7 @@ nv41_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading @@ -531,7 +531,7 @@ nv42_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading @@ -557,7 +557,7 @@ nv43_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading Loading @@ -609,7 +609,7 @@ nv45_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv04_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading Loading @@ -661,7 +661,7 @@ nv47_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading @@ -687,7 +687,7 @@ nv49_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading Loading @@ -739,7 +739,7 @@ nv4b_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, .mc = nv04_mc_new, .mc = nv17_mc_new, .mmu = nv41_mmu_new, .pci = nv40_pci_new, .therm = nv40_therm_new, Loading
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.c +27 −0 Original line number Diff line number Diff line Loading @@ -30,3 +30,30 @@ nv17_mc_reset[] = { { 0x00000002, NVKM_ENGINE_MPEG }, {} }; const struct nvkm_mc_map nv17_mc_intr[] = { { 0x03010000, NVKM_ENGINE_DISP }, { 0x00001000, NVKM_ENGINE_GR }, { 0x00000100, NVKM_ENGINE_FIFO }, { 0x00000001, NVKM_ENGINE_MPEG }, { 0x10000000, NVKM_SUBDEV_BUS }, { 0x00100000, NVKM_SUBDEV_TIMER }, {} }; static const struct nvkm_mc_func nv17_mc = { .init = nv04_mc_init, .intr = nv17_mc_intr, .intr_unarm = nv04_mc_intr_unarm, .intr_rearm = nv04_mc_intr_rearm, .intr_mask = nv04_mc_intr_mask, .reset = nv17_mc_reset, }; int nv17_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) { return nvkm_mc_new_(&nv17_mc, device, index, pmc); }
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c +2 −1 Original line number Diff line number Diff line Loading @@ -40,10 +40,11 @@ nv44_mc_init(struct nvkm_mc *mc) static const struct nvkm_mc_func nv44_mc = { .init = nv44_mc_init, .intr = nv04_mc_intr, .intr = nv17_mc_intr, .intr_unarm = nv04_mc_intr_unarm, .intr_rearm = nv04_mc_intr_rearm, .intr_mask = nv04_mc_intr_mask, .reset = nv17_mc_reset, }; int Loading
drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c +1 −0 Original line number Diff line number Diff line Loading @@ -51,6 +51,7 @@ nv50_mc = { .intr_unarm = nv04_mc_intr_unarm, .intr_rearm = nv04_mc_intr_rearm, .intr_mask = nv04_mc_intr_mask, .reset = nv17_mc_reset, }; int Loading