Commit 7a1c5c67 authored by Jonathan Kim's avatar Jonathan Kim Committed by Alex Deucher
Browse files

drm/amdkfd: enable cooperative groups for gfx11 



MES can concurrently schedule queues on the device that require
exclusive device access if marked exclusively_scheduled without the
requirement of GWS.  Similar to the F32 HWS, MES will manage
quality of service for these queues.
Use this for cooperative groups since cooperative groups are device
occupancy limited.

Since some GFX11 devices can only be debugged with partial CUs, do not
allow the debugging of cooperative groups on these devices as the CU
occupancy limit will change on attach.

In addition, zero initialize the MES add queue submission vector for MES
initialization tests as we do not want these to be cooperative
dispatches.

Signed-off-by: default avatarJonathan Kim <jonathan.kim@amd.com>
Reviewed-by: default avatarFelix Kuehling <felix.kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 83f24a8f

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

+2 −0
Original line number Diff line number Diff line
@@ -642,6 +642,8 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 
	unsigned long flags;

	int r;



	memset(&queue_input, 0, sizeof(struct mes_add_queue_input));



	/* allocate the mes queue buffer */

	queue = kzalloc(sizeof(struct amdgpu_mes_queue), GFP_KERNEL);

	if (!queue) {

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

+1 −0
Original line number Diff line number Diff line
@@ -224,6 +224,7 @@ struct mes_add_queue_input { 
	uint32_t	is_kfd_process;

	uint32_t	is_aql_queue;

	uint32_t	queue_size;

	uint32_t	exclusively_scheduled;

};



struct mes_remove_queue_input {

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+2 −0
Original line number Diff line number Diff line
@@ -214,6 +214,8 @@ static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 
	mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;

	mes_add_queue_pkt.gds_size = input->queue_size;



	mes_add_queue_pkt.exclusively_scheduled = input->exclusively_scheduled;



	return mes_v11_0_submit_pkt_and_poll_completion(mes,

			&mes_add_queue_pkt, sizeof(mes_add_queue_pkt),

			offsetof(union MESAPI__ADD_QUEUE, api_status));

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

+2 −1
Original line number Diff line number Diff line
@@ -1487,7 +1487,8 @@ static int kfd_ioctl_alloc_queue_gws(struct file *filep, 
		goto out_unlock;

	}



	if (!kfd_dbg_has_gws_support(dev) && p->debug_trap_enabled) {

	if (p->debug_trap_enabled && (!kfd_dbg_has_gws_support(dev) ||

				      kfd_dbg_has_cwsr_workaround(dev))) {

		retval = -EBUSY;

		goto out_unlock;

	}

drivers/gpu/drm/amd/amdkfd/kfd_debug.c

+2 −1
Original line number Diff line number Diff line
@@ -753,7 +753,8 @@ int kfd_dbg_trap_enable(struct kfd_process *target, uint32_t fd, 
		if (!KFD_IS_SOC15(pdd->dev))

			return -ENODEV;



		if (!kfd_dbg_has_gws_support(pdd->dev) && pdd->qpd.num_gws)

		if (pdd->qpd.num_gws && (!kfd_dbg_has_gws_support(pdd->dev) ||

					 kfd_dbg_has_cwsr_workaround(pdd->dev)))

			return -EBUSY;

	}