Commit 7b37523f authored by Jessica Zhang's avatar Jessica Zhang Committed by Dmitry Baryshkov
Browse files

drm/msm/dpu: Move MISR methods to dpu_hw_util 



Move layer mixer specific MISR methods to generalized helper methods.
This will make it easier to add CRC support for other blocks in the
future.

Changes since V2:
- Reordered parameters so that offsets are after hw_blk_reg_map
- Fixed mismatched whitespace in bitmask definitions

Signed-off-by: default avatarJessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/490732/
Link: https://lore.kernel.org/r/20220622171835.7558-3-quic_jesszhan@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 58fc5d18

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c

+3 −39
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.

 */
@@ -27,11 +28,6 @@ 


#define LM_MISR_CTRL                     0x310

#define LM_MISR_SIGNATURE                0x314

#define LM_MISR_FRAME_COUNT_MASK         0xFF

#define LM_MISR_CTRL_ENABLE              BIT(8)

#define LM_MISR_CTRL_STATUS              BIT(9)

#define LM_MISR_CTRL_STATUS_CLEAR        BIT(10)

#define LM_MISR_CTRL_FREE_RUN_MASK     BIT(31)





static const struct dpu_lm_cfg *_lm_offset(enum dpu_lm mixer,
@@ -107,44 +103,12 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx, 


static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count)

{

	struct dpu_hw_blk_reg_map *c = &ctx->hw;

	u32 config = 0;



	DPU_REG_WRITE(c, LM_MISR_CTRL, LM_MISR_CTRL_STATUS_CLEAR);



	/* Clear old MISR value (in case it's read before a new value is calculated)*/

	wmb();



	if (enable) {

		config = (frame_count & LM_MISR_FRAME_COUNT_MASK) |

			LM_MISR_CTRL_ENABLE | LM_MISR_CTRL_FREE_RUN_MASK;



		DPU_REG_WRITE(c, LM_MISR_CTRL, config);

	} else {

		DPU_REG_WRITE(c, LM_MISR_CTRL, 0);

	}



	dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count);

}



static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)

{

	struct dpu_hw_blk_reg_map *c = &ctx->hw;

	u32 ctrl = 0;



	if (!misr_value)

		return -EINVAL;



	ctrl = DPU_REG_READ(c, LM_MISR_CTRL);



	if (!(ctrl & LM_MISR_CTRL_ENABLE))

		return -ENODATA;



	if (!(ctrl & LM_MISR_CTRL_STATUS))

		return -EINVAL;



	*misr_value = DPU_REG_READ(c, LM_MISR_SIGNATURE);



	return 0;

	return dpu_hw_collect_misr(&ctx->hw, LM_MISR_CTRL, LM_MISR_SIGNATURE, misr_value);

}



static void dpu_hw_lm_setup_blend_config_combined_alpha(struct dpu_hw_mixer *ctx,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

+48 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

/*

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

 */

#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
@@ -447,3 +449,48 @@ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, 


	return 0;

}



void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,

		u32 misr_ctrl_offset,

		bool enable, u32 frame_count)

{

	u32 config = 0;



	DPU_REG_WRITE(c, misr_ctrl_offset, MISR_CTRL_STATUS_CLEAR);



	/* Clear old MISR value (in case it's read before a new value is calculated)*/

	wmb();



	if (enable) {

		config = (frame_count & MISR_FRAME_COUNT_MASK) |

			MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK;



		DPU_REG_WRITE(c, misr_ctrl_offset, config);

	} else {

		DPU_REG_WRITE(c, misr_ctrl_offset, 0);

	}



}



int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,

		u32 misr_ctrl_offset,

		u32 misr_signature_offset,

		u32 *misr_value)

{

	u32 ctrl = 0;



	if (!misr_value)

		return -EINVAL;



	ctrl = DPU_REG_READ(c, misr_ctrl_offset);



	if (!(ctrl & MISR_CTRL_ENABLE))

		return -ENODATA;



	if (!(ctrl & MISR_CTRL_STATUS))

		return -EINVAL;



	*misr_value = DPU_REG_READ(c, misr_signature_offset);



	return 0;

}

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h

+16 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.

 */
@@ -12,6 +13,11 @@ 
#include "dpu_hw_catalog.h"



#define REG_MASK(n)                     ((BIT(n)) - 1)

#define MISR_FRAME_COUNT_MASK           0xFF

#define MISR_CTRL_ENABLE                BIT(8)

#define MISR_CTRL_STATUS                BIT(9)

#define MISR_CTRL_STATUS_CLEAR          BIT(10)

#define MISR_CTRL_FREE_RUN_MASK         BIT(31)



/*

 * This is the common struct maintained by each sub block
@@ -341,4 +347,14 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, 
u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,

		u32 total_fl);



void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,

		u32 misr_ctrl_offset,

		bool enable,

		u32 frame_count);



int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,

		u32 misr_ctrl_offset,

		u32 misr_signature_offset,

		u32 *misr_value);



#endif /* _DPU_HW_UTIL_H */