Commit 7c4ed1df authored by Joshua Aberback's avatar Joshua Aberback Committed by Alex Deucher
Browse files

drm/amd/display: Copy WM values from set A to other sets in hw_init 



[Why]
When we transfer the WM range table to SMU, they can perform a watermark
switch right away. This can be a problem if we're in not in accelerated mode
during hw_init as SMU may initiate a dummy p-state change before the rest
of the watermarks are programmed. Watermark set A is defined to be
sufficient for all cases, so we can copy the values from set A to all other
sets, avoiding any issues from SMU doing WM switches.

[How]
 - new hubbub func init_watermarks
 - copy register values from set A to all other sets
 - call init_watermarks before calling notify_wm_ranges

Signed-off-by: default avatarJoshua Aberback <joshua.aberback@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3e190955

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c

+43 −0
Original line number Diff line number Diff line
@@ -394,6 +394,48 @@ void hubbub3_force_pstate_change_control(struct hubbub *hubbub, 
			DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, force);

}



/* Copy values from WM set A to all other sets */

void hubbub3_init_watermarks(struct hubbub *hubbub)

{

	struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);

	uint32_t reg;



	reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);

	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);

	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);

	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);



	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);

	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);

	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);

	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);



	reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);

	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);

	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);

	REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);



	reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);

	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);

	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);

	REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);



	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);



	reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);



	reg = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, reg);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, reg);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg);

}



static const struct hubbub_funcs hubbub30_funcs = {

	.update_dchub = hubbub2_update_dchub,

	.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,
@@ -408,6 +450,7 @@ static const struct hubbub_funcs hubbub30_funcs = { 
	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,

	.force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,

	.force_pstate_change_control = hubbub3_force_pstate_change_control,

	.init_watermarks = hubbub3_init_watermarks,

};



void hubbub3_construct(struct dcn20_hubbub *hubbub3,

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h

+2 −0
Original line number Diff line number Diff line
@@ -119,4 +119,6 @@ bool hubbub3_program_watermarks( 
void hubbub3_force_pstate_change_control(struct hubbub *hubbub,

		bool force, bool allow);



void hubbub3_init_watermarks(struct hubbub *hubbub);



#endif

drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h

+2 −0
Original line number Diff line number Diff line
@@ -155,6 +155,8 @@ struct hubbub_funcs { 
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)



	void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);



	void (*init_watermarks)(struct hubbub *hubbub);

#endif

};