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Commit 7c62f299 authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Olof Johansson
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ARM: dts: uniphier: add outer cache controller nodes 



Add L2 cache controller nodes for all the UniPhier SoC DTSI.
Also, add an L3 cache controller node for PH1-Pro5 DTSI.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 3d2ef3b3
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