Commit 7d12a611 authored by Jonathan Cameron's avatar Jonathan Cameron
Browse files

iio: dac: ad5761: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 131497ac ("iio: add ad5761 DAC driver")
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-52-jic23@kernel.org
parent d0c167ce

drivers/iio/dac/ad5761.c

+2 −2
Original line number Diff line number Diff line
@@ -70,13 +70,13 @@ struct ad5761_state { 
	enum ad5761_voltage_range range;



	/*

	 * DMA (thus cache coherency maintenance) requires the

	 * DMA (thus cache coherency maintenance) may require the

	 * transfer buffers to live in their own cache lines.

	 */

	union {

		__be32 d32;

		u8 d8[4];

	} data[3] ____cacheline_aligned;

	} data[3] __aligned(IIO_DMA_MINALIGN);

};



static const struct ad5761_range_params ad5761_range_params[] = {