Commit 7d473f47 authored by Kajol Jain's avatar Kajol Jain Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Move JSON/events to appropriate files for power10 platform 



Move some of the power10 JSON/events to appropriate files.

Fixes: 32daa5d7 ("perf vendor events: Initial JSON/events list for power10 platform")
Signed-off-by: default avatarKajol Jain <kjain@linux.ibm.com>
Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: Disha Goel <disgoel@linux.ibm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org
Link: https://lore.kernel.org/r/20230814112803.1508296-4-kjain@linux.ibm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 4836b9a8

tools/perf/pmu-events/arch/powerpc/power10/cache.json

+0 −45
Original line number Diff line number Diff line 
[

  {

    "EventCode": "0x1003C",

    "EventName": "PM_EXEC_STALL_DMISS_L2L3",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."

  },

  {

    "EventCode": "0x1E054",

    "EventName": "PM_EXEC_STALL_DMISS_L21_L31",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip."

  },

  {

    "EventCode": "0x34054",

    "EventName": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict."

  },

  {

    "EventCode": "0x34056",

    "EventName": "PM_EXEC_STALL_LOAD_FINISH",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the next-to-finish (NTF) instruction merged with another load in the LMQ; cycles in which the NTF instruction is waiting for a data reload for a load miss, but the data comes back with a non-NTF instruction."

  },

  {

    "EventCode": "0x3006C",

    "EventName": "PM_RUN_CYC_SMT2_MODE",

    "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."

  },

  {

    "EventCode": "0x300F4",

    "EventName": "PM_RUN_INST_CMPL_CONC",

    "BriefDescription": "PowerPC instruction completed by this thread when all threads in the core had the run-latch set."

  },

  {

    "EventCode": "0x4C016",

    "EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."

  },

  {

    "EventCode": "0x4D014",

    "EventName": "PM_EXEC_STALL_LOAD",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit."

  },

  {

    "EventCode": "0x4D016",

    "EventName": "PM_EXEC_STALL_PTESYNC",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit."

  },

  {

    "EventCode": "0x401EA",

    "EventName": "PM_THRESH_EXC_128",

    "BriefDescription": "Threshold counter exceeded a value of 128."

  },

  {

    "EventCode": "0x400F6",

    "EventName": "PM_BR_MPRED_CMPL",

tools/perf/pmu-events/arch/powerpc/power10/floating_point.json

0 → 100644
+67 −0
Original line number Diff line number Diff line 
[

  {

    "EventCode": "0x100F4",

    "EventName": "PM_FLOP_CMPL",

    "BriefDescription": "Floating Point Operations Completed. Includes any type. It counts once for each 1, 2, 4 or 8 flop instruction. Use PM_1|2|4|8_FLOP_CMPL events to count flops."

  },

  {

    "EventCode": "0x45050",

    "EventName": "PM_1FLOP_CMPL",

    "BriefDescription": "One floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."

  },

  {

    "EventCode": "0x45052",

    "EventName": "PM_4FLOP_CMPL",

    "BriefDescription": "Four floating point instruction completed (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg)."

  },

  {

    "EventCode": "0x45054",

    "EventName": "PM_FMA_CMPL",

    "BriefDescription": "Two floating point instruction completed (FMA class of instructions: fmadd, fnmadd, fmsub, fnmsub). Scalar instructions only."

  },

  {

    "EventCode": "0x45056",

    "EventName": "PM_SCALAR_FLOP_CMPL",

    "BriefDescription": "Scalar floating point instruction completed."

  },

  {

    "EventCode": "0x4505A",

    "EventName": "PM_SP_FLOP_CMPL",

    "BriefDescription": "Single Precision floating point instruction completed."

  },

  {

    "EventCode": "0x4505C",

    "EventName": "PM_MATH_FLOP_CMPL",

    "BriefDescription": "Math floating point instruction completed."

  },

  {

    "EventCode": "0x4D052",

    "EventName": "PM_2FLOP_CMPL",

    "BriefDescription": "Double Precision vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg completed."

  },

  {

    "EventCode": "0x4D054",

    "EventName": "PM_8FLOP_CMPL",

    "BriefDescription": "Four Double Precision vector instruction completed."

  },

  {

    "EventCode": "0x4D056",

    "EventName": "PM_NON_FMA_FLOP_CMPL",

    "BriefDescription": "Non FMA instruction completed."

  },

  {

    "EventCode": "0x4D058",

    "EventName": "PM_VECTOR_FLOP_CMPL",

    "BriefDescription": "Vector floating point instruction completed."

  },

  {

    "EventCode": "0x4D05A",

    "EventName": "PM_NON_MATH_FLOP_CMPL",

    "BriefDescription": "Non Math instruction completed."

  },

  {

    "EventCode": "0x4D05C",

    "EventName": "PM_DPP_FLOP_CMPL",

    "BriefDescription": "Double-Precision or Quad-Precision instruction completed."

  }

]

tools/perf/pmu-events/arch/powerpc/power10/frontend.json

+0 −180
Original line number Diff line number Diff line 
[

  {

    "EventCode": "0x10004",

    "EventName": "PM_EXEC_STALL_TRANSLATION",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss or ERAT miss and waited for it to resolve."

  },

  {

    "EventCode": "0x10006",

    "EventName": "PM_DISP_STALL_HELD_OTHER_CYC",

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any other reason."

  },

  {

    "EventCode": "0x10010",

    "EventName": "PM_PMC4_OVERFLOW",

    "BriefDescription": "The event selected for PMC4 caused the event counter to overflow."

  },

  {

    "EventCode": "0x10020",

    "EventName": "PM_PMC4_REWIND",

    "BriefDescription": "The speculative event selected for PMC4 rewinds and the counter for PMC4 is not charged."

  },

  {

    "EventCode": "0x10038",

    "EventName": "PM_DISP_STALL_TRANSLATION",

    "BriefDescription": "Cycles when dispatch was stalled for this thread because the MMU was handling a translation miss."

  },

  {

    "EventCode": "0x1003A",

    "EventName": "PM_DISP_STALL_BR_MPRED_IC_L2",

    "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2 after suffering a branch mispredict."

  },

  {

    "EventCode": "0x1D05E",

    "EventName": "PM_DISP_STALL_HELD_HALT_CYC",

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of power management."

  },

  {

    "EventCode": "0x1E050",

    "EventName": "PM_DISP_STALL_HELD_STF_MAPPER_CYC",

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the STF mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR."

  },

  {

    "EventCode": "0x1F054",

    "EventName": "PM_DTLB_HIT",

    "BriefDescription": "The PTE required by the instruction was resident in the TLB (data TLB access). When MMCR1[16]=0 this event counts only demand hits. When MMCR1[16]=1 this event includes demand and prefetch. Applies to both HPT and RPT."

  },

  {

    "EventCode": "0x10064",

    "EventName": "PM_DISP_STALL_IC_L2",

    "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L2."

  },

  {

    "EventCode": "0x101E8",

    "EventName": "PM_THRESH_EXC_256",

    "BriefDescription": "Threshold counter exceeded a count of 256."

  },

  {

    "EventCode": "0x101EC",

    "EventName": "PM_THRESH_MET",

    "BriefDescription": "Threshold exceeded."

  },

  {

    "EventCode": "0x100F2",

    "EventName": "PM_1PLUS_PPC_CMPL",
@@ -69,56 +14,6 @@ 
    "EventName": "PM_IERAT_MISS",

    "BriefDescription": "IERAT Reloaded to satisfy an IERAT miss. All page sizes are counted by this event. This event only counts instruction demand access."

  },

  {

    "EventCode": "0x100F8",

    "EventName": "PM_DISP_STALL_CYC",

    "BriefDescription": "Cycles the ICT has no itags assigned to this thread (no instructions were dispatched during these cycles)."

  },

  {

    "EventCode": "0x20006",

    "EventName": "PM_DISP_STALL_HELD_ISSQ_FULL_CYC",

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch due to Issue queue full. Includes issue queue and branch queue."

  },

  {

    "EventCode": "0x20114",

    "EventName": "PM_MRK_L2_RC_DISP",

    "BriefDescription": "Marked instruction RC dispatched in L2."

  },

  {

    "EventCode": "0x2C010",

    "EventName": "PM_EXEC_STALL_LSU",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the Load Store Unit. This does not include simple fixed point instructions."

  },

  {

    "EventCode": "0x2C016",

    "EventName": "PM_DISP_STALL_IERAT_ONLY_MISS",

    "BriefDescription": "Cycles when dispatch was stalled while waiting to resolve an instruction ERAT miss."

  },

  {

    "EventCode": "0x2C01E",

    "EventName": "PM_DISP_STALL_BR_MPRED_IC_L3",

    "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3 after suffering a branch mispredict."

  },

  {

    "EventCode": "0x2D01A",

    "EventName": "PM_DISP_STALL_IC_MISS",

    "BriefDescription": "Cycles when dispatch was stalled for this thread due to an instruction cache miss."

  },

  {

    "EventCode": "0x2E018",

    "EventName": "PM_DISP_STALL_FETCH",

    "BriefDescription": "Cycles when dispatch was stalled for this thread because Fetch was being held."

  },

  {

    "EventCode": "0x2E01A",

    "EventName": "PM_DISP_STALL_HELD_XVFC_MAPPER_CYC",

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the XVFC mapper/SRB was full."

  },

  {

    "EventCode": "0x2C142",

    "EventName": "PM_MRK_XFER_FROM_SRC_PMC2",

    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."

  },

  {

    "EventCode": "0x24050",

    "EventName": "PM_IOPS_DISP",
@@ -134,11 +29,6 @@ 
    "EventName": "PM_BR_TAKEN_CMPL",

    "BriefDescription": "Branch Taken instruction completed."

  },

  {

    "EventCode": "0x30004",

    "EventName": "PM_DISP_STALL_FLUSH",

    "BriefDescription": "Cycles when dispatch was stalled because of a flush that happened to an instruction(s) that was not yet next-to-complete (NTC). PM_EXEC_STALL_NTC_FLUSH only includes instructions that were flushed after becoming NTC."

  },

  {

    "EventCode": "0x3000A",

    "EventName": "PM_DISP_STALL_ITLB_MISS",
@@ -149,56 +39,16 @@ 
    "EventName": "PM_FLUSH_COMPLETION",

    "BriefDescription": "The instruction that was next to complete (oldest in the pipeline) did not complete because it suffered a flush."

  },

  {

    "EventCode": "0x30014",

    "EventName": "PM_EXEC_STALL_STORE",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store instruction executing in the Load Store Unit."

  },

  {

    "EventCode": "0x30018",

    "EventName": "PM_DISP_STALL_HELD_SCOREBOARD_CYC",

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."

  },

  {

    "EventCode": "0x30026",

    "EventName": "PM_EXEC_STALL_STORE_MISS",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a store whose cache line was not resident in the L1 and was waiting for allocation of the missing line into the L1."

  },

  {

    "EventCode": "0x3012A",

    "EventName": "PM_MRK_L2_RC_DONE",

    "BriefDescription": "L2 RC machine completed the transaction for the marked instruction."

  },

  {

    "EventCode": "0x3F046",

    "EventName": "PM_ITLB_HIT_1G",

    "BriefDescription": "Instruction TLB hit (IERAT reload) page size 1G, which implies Radix Page Table translation is in use. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."

  },

  {

    "EventCode": "0x34058",

    "EventName": "PM_DISP_STALL_BR_MPRED_ICMISS",

    "BriefDescription": "Cycles when dispatch was stalled after a mispredicted branch resulted in an instruction cache miss."

  },

  {

    "EventCode": "0x3D05C",

    "EventName": "PM_DISP_STALL_HELD_RENAME_CYC",

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because the mapper/SRB was full. Includes GPR (count, link, tar), VSR, VMR, FPR and XVFC."

  },

  {

    "EventCode": "0x3E052",

    "EventName": "PM_DISP_STALL_IC_L3",

    "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from the local L3."

  },

  {

    "EventCode": "0x3E054",

    "EventName": "PM_LD_MISS_L1",

    "BriefDescription": "Load missed L1, counted at finish time. LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."

  },

  {

    "EventCode": "0x301EA",

    "EventName": "PM_THRESH_EXC_1024",

    "BriefDescription": "Threshold counter exceeded a value of 1024."

  },

  {

    "EventCode": "0x300FA",

    "EventName": "PM_INST_FROM_L3MISS",
@@ -209,36 +59,6 @@ 
    "EventName": "PM_ISSUE_KILL",

    "BriefDescription": "Cycles in which an instruction or group of instructions were cancelled after being issued. This event increments once per occurrence, regardless of how many instructions are included in the issue group."

  },

  {

    "EventCode": "0x40116",

    "EventName": "PM_MRK_LARX_FIN",

    "BriefDescription": "Marked load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."

  },

  {

    "EventCode": "0x4C010",

    "EventName": "PM_DISP_STALL_BR_MPRED_IC_L3MISS",

    "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from sources beyond the local L3 after suffering a mispredicted branch."

  },

  {

    "EventCode": "0x4D01E",

    "EventName": "PM_DISP_STALL_BR_MPRED",

    "BriefDescription": "Cycles when dispatch was stalled for this thread due to a mispredicted branch."

  },

  {

    "EventCode": "0x4E010",

    "EventName": "PM_DISP_STALL_IC_L3MISS",

    "BriefDescription": "Cycles when dispatch was stalled while the instruction was fetched from any source beyond the local L3."

  },

  {

    "EventCode": "0x4E01A",

    "EventName": "PM_DISP_STALL_HELD_CYC",

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch for any reason."

  },

  {

    "EventCode": "0x4003C",

    "EventName": "PM_DISP_STALL_HELD_SYNC_CYC",

    "BriefDescription": "Cycles in which the next-to-complete (NTC) instruction is held at dispatch because of a synchronizing instruction that requires the ICT to be empty before dispatch."

  },

  {

    "EventCode": "0x44056",

    "EventName": "PM_VECTOR_ST_CMPL",

tools/perf/pmu-events/arch/powerpc/power10/marked.json

+148 −38

File changed.

Preview size limit exceeded, changes collapsed.

tools/perf/pmu-events/arch/powerpc/power10/memory.json

+0 −85
Original line number Diff line number Diff line 
[

  {

    "EventCode": "0x1000A",

    "EventName": "PM_PMC3_REWIND",

    "BriefDescription": "The speculative event selected for PMC3 rewinds and the counter for PMC3 is not charged."

  },

  {

    "EventCode": "0x1C040",

    "EventName": "PM_XFER_FROM_SRC_PMC1",

    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."

  },

  {

    "EventCode": "0x1C142",

    "EventName": "PM_MRK_XFER_FROM_SRC_PMC1",

    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."

  },

  {

    "EventCode": "0x1C144",

    "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC1",

    "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[0:12]."

  },

  {

    "EventCode": "0x1C056",

    "EventName": "PM_DERAT_MISS_4K",
@@ -34,26 +19,11 @@ 
    "EventName": "PM_DTLB_MISS_2M",

    "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."

  },

  {

    "EventCode": "0x1E056",

    "EventName": "PM_EXEC_STALL_STORE_PIPE",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline was executing in the store unit. This does not include cycles spent handling store misses, PTESYNC instructions or TLBIE instructions."

  },

  {

    "EventCode": "0x1F150",

    "EventName": "PM_MRK_ST_L2_CYC",

    "BriefDescription": "Cycles from L2 RC dispatch to L2 RC completion."

  },

  {

    "EventCode": "0x10062",

    "EventName": "PM_LD_L3MISS_PEND_CYC",

    "BriefDescription": "Cycles in which an L3 miss was pending for this thread."

  },

  {

    "EventCode": "0x20010",

    "EventName": "PM_PMC1_OVERFLOW",

    "BriefDescription": "The event selected for PMC1 caused the event counter to overflow."

  },

  {

    "EventCode": "0x2001A",

    "EventName": "PM_ITLB_HIT",
@@ -79,36 +49,16 @@ 
    "EventName": "PM_DTLB_MISS_4K",

    "BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."

  },

  {

    "EventCode": "0x2D154",

    "EventName": "PM_MRK_DERAT_MISS_64K",

    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."

  },

  {

    "EventCode": "0x200F6",

    "EventName": "PM_DERAT_MISS",

    "BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."

  },

  {

    "EventCode": "0x30016",

    "EventName": "PM_EXEC_STALL_DERAT_DTLB_MISS",

    "BriefDescription": "Cycles in which the oldest instruction in the pipeline suffered a TLB miss and waited for it resolve."

  },

  {

    "EventCode": "0x3C040",

    "EventName": "PM_XFER_FROM_SRC_PMC3",

    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."

  },

  {

    "EventCode": "0x3C142",

    "EventName": "PM_MRK_XFER_FROM_SRC_PMC3",

    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."

  },

  {

    "EventCode": "0x3C144",

    "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC3",

    "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[30:42]."

  },

  {

    "EventCode": "0x3C054",

    "EventName": "PM_DERAT_MISS_16M",
@@ -124,21 +74,11 @@ 
    "EventName": "PM_LARX_FIN",

    "BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."

  },

  {

    "EventCode": "0x301E2",

    "EventName": "PM_MRK_ST_CMPL",

    "BriefDescription": "Marked store completed and sent to nest. Note that this count excludes cache-inhibited stores."

  },

  {

    "EventCode": "0x300FC",

    "EventName": "PM_DTLB_MISS",

    "BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. This event only counts for demand misses."

  },

  {

    "EventCode": "0x4D02C",

    "EventName": "PM_PMC1_REWIND",

    "BriefDescription": "The speculative event selected for PMC1 rewinds and the counter for PMC1 is not charged."

  },

  {

    "EventCode": "0x4003E",

    "EventName": "PM_LD_CMPL",
@@ -149,16 +89,6 @@ 
    "EventName": "PM_XFER_FROM_SRC_PMC4",

    "BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."

  },

  {

    "EventCode": "0x4C142",

    "EventName": "PM_MRK_XFER_FROM_SRC_PMC4",

    "BriefDescription": "For a marked data transfer instruction, the processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."

  },

  {

    "EventCode": "0x4C144",

    "EventName": "PM_MRK_XFER_FROM_SRC_CYC_PMC4",

    "BriefDescription": "Cycles taken for a marked demand miss to reload a line from the source specified in MMCR3[45:57]."

  },

  {

    "EventCode": "0x4C056",

    "EventName": "PM_DTLB_MISS_16M",
@@ -168,20 +98,5 @@ 
    "EventCode": "0x4C05A",

    "EventName": "PM_DTLB_MISS_1G",

    "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."

  },

  {

    "EventCode": "0x4C15E",

    "EventName": "PM_MRK_DTLB_MISS_64K",

    "BriefDescription": "Marked Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."

  },

  {

    "EventCode": "0x4D056",

    "EventName": "PM_NON_FMA_FLOP_CMPL",

    "BriefDescription": "Non FMA instruction completed."

  },

  {

    "EventCode": "0x40164",

    "EventName": "PM_MRK_DERAT_MISS_2M",

    "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M for a marked instruction. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."

  }

]