Commit 8065c0e1 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'yt8531-support'



Frank Sae says:

====================
net: add dts for yt8521 and yt8531s, add driver for yt8531

Add dts for yt8521 and yt8531s, add driver for yt8531.
 These patches have been verified on our AM335x platform (motherboard)
 which has one integrated yt8521 and one RGMII interface.
 It can connect to daughter boards like yt8531s or yt8531 board.

 v5:
 - change the compatible of yaml
 - change the maintainers of yaml from "frank sae" to "Frank Sae"

 v4:
 - change default tx delay from 150ps to 1950ps
 - add compatible for yaml

 v3:
 - change default rx delay from 1900ps to 1950ps
 - moved ytphy_rgmii_clk_delay_config_with_lock from yt8521's patch to yt8531's patch
 - removed unnecessary checks of phydev->attached_dev->dev_addr

 v2:
 - split BIT macro as one patch
 - split "dts for yt8521/yt8531s ... " patch as two patches
 - use standard rx-internal-delay-ps and tx-internal-delay-ps, removed motorcomm,sds-tx-amplitude
 - removed ytphy_parse_dt, ytphy_probe_helper and ytphy_config_init_helper
 - not store dts arg to yt8521_priv
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 18390581 4ac94f72
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MotorComm yt8xxx Ethernet PHY

maintainers:
  - Frank Sae <frank.sae@motor-comm.com>

allOf:
  - $ref: ethernet-phy.yaml#

properties:
  compatible:
    enum:
      - ethernet-phy-id4f51.e91a
      - ethernet-phy-id4f51.e91b

  rx-internal-delay-ps:
    description: |
      RGMII RX Clock Delay used only when PHY operates in RGMII mode with
      internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
    enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650,
            1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800,
            2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ]
    default: 1950

  tx-internal-delay-ps:
    description: |
      RGMII TX Clock Delay used only when PHY operates in RGMII mode with
      internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
    enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800,
            1950, 2100, 2250 ]
    default: 1950

  motorcomm,clk-out-frequency-hz:
    description: clock output on clock output pin.
    enum: [0, 25000000, 125000000]
    default: 0

  motorcomm,keep-pll-enabled:
    description: |
      If set, keep the PLL enabled even if there is no link. Useful if you
      want to use the clock output without an ethernet link.
    type: boolean

  motorcomm,auto-sleep-disabled:
    description: |
      If set, PHY will not enter sleep mode and close AFE after unplug cable
      for a timer.
    type: boolean

  motorcomm,tx-clk-adj-enabled:
    description: |
      This configuration is mainly to adapt to VF2 with JH7110 SoC.
      Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk.
    type: boolean

  motorcomm,tx-clk-10-inverted:
    description: |
      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
      Transmit PHY Clock delay train configuration when speed is 10Mbps.
    type: boolean

  motorcomm,tx-clk-100-inverted:
    description: |
      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
      Transmit PHY Clock delay train configuration when speed is 100Mbps.
    type: boolean

  motorcomm,tx-clk-1000-inverted:
    description: |
      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
      Transmit PHY Clock delay train configuration when speed is 1000Mbps.
    type: boolean

unevaluatedProperties: false

examples:
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy-mode = "rgmii-id";
        ethernet-phy@4 {
            /*  Only needed to make DT lint tools work. Do not copy/paste
             *  into real DTS files.
             */
            compatible = "ethernet-phy-id4f51.e91a";

            reg = <4>;
            rx-internal-delay-ps = <2100>;
            tx-internal-delay-ps = <150>;
            motorcomm,clk-out-frequency-hz = <0>;
            motorcomm,keep-pll-enabled;
            motorcomm,auto-sleep-disabled;
        };
    };
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy-mode = "rgmii";
        ethernet-phy@5 {
            /*  Only needed to make DT lint tools work. Do not copy/paste
             *  into real DTS files.
             */
            compatible = "ethernet-phy-id4f51.e91a";

            reg = <5>;
            motorcomm,clk-out-frequency-hz = <125000000>;
            motorcomm,keep-pll-enabled;
            motorcomm,auto-sleep-disabled;
        };
    };
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@@ -847,6 +847,8 @@ patternProperties:
    description: Moortec Semiconductor Ltd.
  "^mosaixtech,.*":
    description: Mosaix Technologies, Inc.
  "^motorcomm,.*":
    description: MotorComm, Inc.
  "^motorola,.*":
    description: Motorola, Inc.
  "^moxa,.*":
+1 −0
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@@ -14170,6 +14170,7 @@ M: Peter Geis <pgwipeout@gmail.com>
M:	Frank <Frank.Sae@motor-comm.com>
L:	netdev@vger.kernel.org
S:	Maintained
F:	Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml
F:	drivers/net/phy/motorcomm.c
MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD
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@@ -257,7 +257,7 @@ config MOTORCOMM_PHY
	tristate "Motorcomm PHYs"
	help
	  Enables support for Motorcomm network PHYs.
	  Currently supports the YT8511, YT8521, YT8531S Gigabit Ethernet PHYs.
	  Currently supports YT85xx Gigabit Ethernet PHYs.

config NATIONAL_PHY
	tristate "National Semiconductor PHYs"
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