Commit 82119db8 authored by Hui Tang's avatar Hui Tang Committed by Herbert Xu
Browse files

crypto: hisilicon/hpre - use 'GENMASK' to generate mask value 



Use 'GENMASK' to generate mask value, just make the code clearer.

Signed-off-by: default avatarHui Tang <tanghui20@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 58be5ce3

drivers/crypto/hisilicon/hpre/hpre_crypto.c

+3 −3
Original line number Diff line number Diff line
@@ -330,9 +330,9 @@ static int hpre_alg_res_post_hf(struct hpre_ctx *ctx, struct hpre_sqe *sqe, 


#define HPRE_NO_HW_ERR		0

#define HPRE_HW_TASK_DONE	3

#define HREE_HW_ERR_MASK	0x7ff

#define HREE_SQE_DONE_MASK	0x3

#define HREE_ALG_TYPE_MASK	0x1f

#define HREE_HW_ERR_MASK	GENMASK(10, 0)

#define HREE_SQE_DONE_MASK	GENMASK(1, 0)

#define HREE_ALG_TYPE_MASK	GENMASK(4, 0)

	id = (int)le16_to_cpu(sqe->tag);

	req = ctx->req_list[id];

	hpre_rm_req_from_ctx(req);

drivers/crypto/hisilicon/hpre/hpre_main.c

+7 −7
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ 
#define HPRE_INT_MASK			0x301400

#define HPRE_INT_STATUS			0x301800

#define HPRE_CORE_INT_ENABLE		0

#define HPRE_CORE_INT_DISABLE		0x003fffff

#define HPRE_CORE_INT_DISABLE		GENMASK(21, 0)

#define HPRE_RDCHN_INI_ST		0x301a00

#define HPRE_CLSTR_BASE			0x302000

#define HPRE_CORE_EN_OFFSET		0x04
@@ -69,12 +69,12 @@ 
#define HPRE_DBGFS_VAL_MAX_LEN		20

#define HPRE_PCI_DEVICE_ID		0xa258

#define HPRE_PCI_VF_DEVICE_ID		0xa259

#define HPRE_QM_USR_CFG_MASK		0xfffffffe

#define HPRE_QM_AXI_CFG_MASK		0xffff

#define HPRE_QM_VFG_AX_MASK		0xff

#define HPRE_BD_USR_MASK		0x3

#define HPRE_CLUSTER_CORE_MASK_V2	0xf

#define HPRE_CLUSTER_CORE_MASK_V3	0xff

#define HPRE_QM_USR_CFG_MASK		GENMASK(31, 1)

#define HPRE_QM_AXI_CFG_MASK		GENMASK(15, 0)

#define HPRE_QM_VFG_AX_MASK		GENMASK(7, 0)

#define HPRE_BD_USR_MASK		GENMASK(1, 0)

#define HPRE_CLUSTER_CORE_MASK_V2	GENMASK(3, 0)

#define HPRE_CLUSTER_CORE_MASK_V3	GENMASK(7, 0)



#define HPRE_AM_OOO_SHUTDOWN_ENB	0x301044

#define HPRE_AM_OOO_SHUTDOWN_ENABLE	BIT(0)