Commit 825d1508 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'cxl-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm 



Pull initial support for CXL (Compute Express Link) from Dan Williams:
 "Introduce an initial driver for CXL 2.0 Type-3 Memory Devices.

  CXL is Compute Express Link which released the 2.0 specification in
  November. The Linux relevant changes in CXL 2.0 are support for an OS
  to dynamically assign address space to memory devices, support for
  switches, persistent memory, and hotplug.

  A Type-3 Memory Device is a PCI enumerated device presenting the CXL
  Memory Device Class Code and implementing the CXL.mem protocol.
  CXL.mem allows device to advertise CPU and I/O coherent memory to the
  system, i.e. typical "System RAM" and "Persistent Memory" in Linux
  /proc/iomem terms.

  In addition to the CXL.mem fast path there is an administrative
  command hardware mailbox interface for maintenance and provisioning.
  It is this command interface that is the focus of the initial driver.
  With this driver a CXL device that is mapped by the BIOS can be
  administered by Linux.

  Linux support for CXL PMEM and dynamic CXL address space management
  are to be implemented post v5.12"

Reviewed-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
  4cdadfd5 ("cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints")
  13237183 ("cxl/mem: Add a "RAW" send command")
  472b1ce6 ("cxl/mem: Enable commands via CEL")
  57ee605b ("cxl/mem: Add set of informational commands")

Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
  8adaf747 ("cxl/mem: Find device capabilities")
  b39cb105 ("cxl/mem: Register CXL memX devices")

* tag 'cxl-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm:
  cxl/mem: Fix potential memory leak
  cxl/mem: Return -EFAULT if copy_to_user() fails
  MAINTAINERS: Add maintainers of the CXL driver
  cxl/mem: Add set of informational commands
  cxl/mem: Enable commands via CEL
  cxl/mem: Add a "RAW" send command
  cxl/mem: Add basic IOCTL interface
  cxl/mem: Register CXL memX devices
  cxl/mem: Find device capabilities
  cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints
parents fb9f0854 88ff5d46

.clang-format

+1 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ ForEachMacros: 
  - 'css_for_each_child'

  - 'css_for_each_descendant_post'

  - 'css_for_each_descendant_pre'

  - 'cxl_for_each_cmd'

  - 'device_for_each_child_node'

  - 'dma_fence_chain_for_each'

  - 'do_for_each_ftrace_op'

Documentation/ABI/testing/sysfs-bus-cxl

0 → 100644
+26 −0
Original line number Diff line number Diff line 
What:		/sys/bus/cxl/devices/memX/firmware_version

Date:		December, 2020

KernelVersion:	v5.12

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) "FW Revision" string as reported by the Identify

		Memory Device Output Payload in the CXL-2.0

		specification.



What:		/sys/bus/cxl/devices/memX/ram/size

Date:		December, 2020

KernelVersion:	v5.12

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) "Volatile Only Capacity" as bytes. Represents the

		identically named field in the Identify Memory Device Output

		Payload in the CXL-2.0 specification.



What:		/sys/bus/cxl/devices/memX/pmem/size

Date:		December, 2020

KernelVersion:	v5.12

Contact:	linux-cxl@vger.kernel.org

Description:

		(RO) "Persistent Only Capacity" as bytes. Represents the

		identically named field in the Identify Memory Device Output

		Payload in the CXL-2.0 specification.

Documentation/driver-api/cxl/index.rst

0 → 100644
+12 −0
Original line number Diff line number Diff line 
.. SPDX-License-Identifier: GPL-2.0



====================

Compute Express Link

====================



.. toctree::

   :maxdepth: 1



   memory-devices



.. only::  subproject and html

Documentation/driver-api/cxl/memory-devices.rst

0 → 100644
+46 −0
Original line number Diff line number Diff line 
.. SPDX-License-Identifier: GPL-2.0

.. include:: <isonum.txt>



===================================

Compute Express Link Memory Devices

===================================



A Compute Express Link Memory Device is a CXL component that implements the

CXL.mem protocol. It contains some amount of volatile memory, persistent memory,

or both. It is enumerated as a PCI device for configuration and passing

messages over an MMIO mailbox. Its contribution to the System Physical

Address space is handled via HDM (Host Managed Device Memory) decoders

that optionally define a device's contribution to an interleaved address

range across multiple devices underneath a host-bridge or interleaved

across host-bridges.



Driver Infrastructure

=====================



This section covers the driver infrastructure for a CXL memory device.



CXL Memory Device

-----------------



.. kernel-doc:: drivers/cxl/mem.c

   :doc: cxl mem



.. kernel-doc:: drivers/cxl/mem.c

   :internal:



CXL Bus

-------

.. kernel-doc:: drivers/cxl/bus.c

   :doc: cxl bus



External Interfaces

===================



CXL IOCTL Interface

-------------------



.. kernel-doc:: include/uapi/linux/cxl_mem.h

   :doc: UAPI



.. kernel-doc:: include/uapi/linux/cxl_mem.h

   :internal:

Documentation/driver-api/index.rst

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ available subsections can be seen below. 
   usb/index

   firewire

   pci/index

   cxl/index

   spi

   i2c

   ipmb