Commit 82ab97c8 authored by Sakari Ailus's avatar Sakari Ailus Committed by Mauro Carvalho Chehab
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media: ccs-pll: Fix check for PLL multiplier upper bound 



The additional multiplier (for higher VT timing) of the PLL multiplier was
checked against the upper limit but the result was rounded up, possibly
producing too high additional multiplier. Round down instead to keep
within hardware limits.

Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent c64cf71d

drivers/media/i2c/ccs-pll.c

+1 −2
Original line number Diff line number Diff line
@@ -204,8 +204,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, 
	dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",

		more_mul_max);

	/* Ensure we won't go above max_pll_multiplier. */

	more_mul_max = min(more_mul_max,

			   DIV_ROUND_UP(op_lim_fr->max_pll_multiplier, mul));

	more_mul_max = min(more_mul_max, op_lim_fr->max_pll_multiplier / mul);

	dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",

		more_mul_max);