Commit 83f83cc0 authored by Shaokun Zhang's avatar Shaokun Zhang Committed by Will Deacon
Browse files

arm64: perf: Expose some Armv9 common events under sysfs 

Armv9[1] has introduced some common architectural events (0x400C-0x400F)
and common microarchitectural events (0x4010-0x401B), which can be detected
by PMCEID0_EL0 from bit44 to bit59, so expose these common events under
sysfs.

[1] https://developer.arm.com/documentation/ddi0608/ba



Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: default avatarShaokun Zhang <zhangshaokun@hisilicon.com>
Link: https://lore.kernel.org/r/20220303085419.64085-1-zhangshaokun@hisilicon.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 68fa55f0

arch/arm64/include/asm/perf_event.h

+14 −0
Original line number Diff line number Diff line
@@ -96,6 +96,20 @@ 
#define	ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS			0x400A

#define	ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD			0x400B



/* Trace buffer events */

#define ARMV8_PMUV3_PERFCTR_TRB_WRAP				0x400C

#define ARMV8_PMUV3_PERFCTR_TRB_TRIG				0x400E



/* Trace unit events */

#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT0				0x4010

#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT1				0x4011

#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT2				0x4012

#define ARMV8_PMUV3_PERFCTR_TRCEXTOUT3				0x4013

#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4			0x4018

#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5			0x4019

#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6			0x401A

#define ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7			0x401B



/* additional latency from alignment events */

#define	ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT			0x4020

#define	ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT			0x4021

arch/arm64/kernel/perf_event.c

+10 −0
Original line number Diff line number Diff line
@@ -242,6 +242,16 @@ static struct attribute *armv8_pmuv3_event_attrs[] = { 
	ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),

	ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),

	ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),

	ARMV8_EVENT_ATTR(trb_wrap, ARMV8_PMUV3_PERFCTR_TRB_WRAP),

	ARMV8_EVENT_ATTR(trb_trig, ARMV8_PMUV3_PERFCTR_TRB_TRIG),

	ARMV8_EVENT_ATTR(trcextout0, ARMV8_PMUV3_PERFCTR_TRCEXTOUT0),

	ARMV8_EVENT_ATTR(trcextout1, ARMV8_PMUV3_PERFCTR_TRCEXTOUT1),

	ARMV8_EVENT_ATTR(trcextout2, ARMV8_PMUV3_PERFCTR_TRCEXTOUT2),

	ARMV8_EVENT_ATTR(trcextout3, ARMV8_PMUV3_PERFCTR_TRCEXTOUT3),

	ARMV8_EVENT_ATTR(cti_trigout4, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4),

	ARMV8_EVENT_ATTR(cti_trigout5, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5),

	ARMV8_EVENT_ATTR(cti_trigout6, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6),

	ARMV8_EVENT_ATTR(cti_trigout7, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7),

	ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),

	ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),

	ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),