Commit 857aa2be authored by Mustapha Ghaddar's avatar Mustapha Ghaddar Committed by Alex Deucher
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drm/amd/display: Update BW alloc after new DMUB logic



[WHY]
After introducing new DPIA NOTIFICATION we will need
to update the exiting BW allocation logic

[HOW]
Updated the BW alloc source and header files

Tested-by: default avatarDaniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: default avatarMeenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarMustapha Ghaddar <mghaddar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6b8701be
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+1 −1
Original line number Original line Diff line number Diff line
@@ -158,11 +158,11 @@ struct dc_panel_config {
struct dc_dpia_bw_alloc {
struct dc_dpia_bw_alloc {
	int sink_verified_bw;  // The Verified BW that sink can allocated and use that has been verified already
	int sink_verified_bw;  // The Verified BW that sink can allocated and use that has been verified already
	int sink_allocated_bw; // The Actual Allocated BW that sink currently allocated
	int sink_allocated_bw; // The Actual Allocated BW that sink currently allocated
	int padding_bw;        // The Padding "Un-used" BW allocated by CM for padding reasons
	int sink_max_bw;       // The Max BW that sink can require/support
	int sink_max_bw;       // The Max BW that sink can require/support
	int estimated_bw;      // The estimated available BW for this DPIA
	int estimated_bw;      // The estimated available BW for this DPIA
	int bw_granularity;    // BW Granularity
	int bw_granularity;    // BW Granularity
	bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3:  DP-Tx & Dpia & CM
	bool bw_alloc_enabled; // The BW Alloc Mode Support is turned ON for all 3:  DP-Tx & Dpia & CM
	bool response_ready;   // Response ready from the CM side
};
};


/*
/*
+39 −8
Original line number Original line Diff line number Diff line
@@ -26,13 +26,13 @@
#ifndef DC_INC_LINK_DP_DPIA_BW_H_
#ifndef DC_INC_LINK_DP_DPIA_BW_H_
#define DC_INC_LINK_DP_DPIA_BW_H_
#define DC_INC_LINK_DP_DPIA_BW_H_


// XXX: TODO: Re-add for Phase 2
/*
/* Number of Host Routers per motherboard is 2 and 2 DPIA per host router */
 * Host Router BW type
#define MAX_HR_NUM 2
 */

enum bw_type {
struct dc_host_router_bw_alloc {
	HOST_ROUTER_BW_ESTIMATED,
	int max_bw[MAX_HR_NUM];             // The Max BW that each Host Router has available to be shared btw DPIAs
	HOST_ROUTER_BW_ALLOCATED,
	int total_estimated_bw[MAX_HR_NUM]; // The Total Verified and available BW that Host Router has
	HOST_ROUTER_BW_INVALID,
};
};


/*
/*
@@ -61,9 +61,40 @@ void set_usb4_req_bw_req(struct dc_link *link, int req_bw);
 * find out the result of allocating on CM and update structs accordingly
 * find out the result of allocating on CM and update structs accordingly
 *
 *
 * @link: pointer to the dc_link struct instance
 * @link: pointer to the dc_link struct instance
 * @bw: Allocated or Estimated BW depending on the result
 * @result: Response type
 *
 * return: none
 */
void get_usb4_req_bw_resp(struct dc_link *link, uint8_t bw, uint8_t result);

/*
 * Return the response_ready flag from dc_link struct
 *
 * @link: pointer to the dc_link struct instance
 *
 * return: response_ready flag from dc_link struct
 */
bool get_cm_response_ready_flag(struct dc_link *link);

/*
 * Get the Max Available BW or Max Estimated BW for each Host Router
 *
 * @link: pointer to the dc_link struct instance
 * @type: ESTIMATD BW or MAX AVAILABLE BW
 *
 * return: response_ready flag from dc_link struct
 */
int get_host_router_total_bw(struct dc_link *link, uint8_t type);

/*
 * Cleanup function for when the dpia is unplugged to reset struct
 * and perform any required clean up
 *
 * @link: pointer to the dc_link struct instance
 *
 *
 * return: none
 * return: none
 */
 */
void get_usb4_req_bw_resp(struct dc_link *link);
bool dpia_bw_alloc_unplug(struct dc_link *link);


#endif /* DC_INC_LINK_DP_DPIA_BW_H_ */
#endif /* DC_INC_LINK_DP_DPIA_BW_H_ */
+9 −9
Original line number Original line Diff line number Diff line
@@ -98,20 +98,20 @@ enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,


		if (cmd.dpia_notify.payload.header.type == DPIA_NOTIFY__BW_ALLOCATION) {
		if (cmd.dpia_notify.payload.header.type == DPIA_NOTIFY__BW_ALLOCATION) {


			if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_failed) {
			notify->bw_alloc_reply.estimated_bw =
				notify->result = DPIA_BW_REQ_FAILED;
					cmd.dpia_notify.payload.data.dpia_bw_alloc.estimated_bw;
			} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_succeeded) {
				notify->result = DPIA_BW_REQ_SUCCESS;
			notify->bw_alloc_reply.allocated_bw =
			notify->bw_alloc_reply.allocated_bw =
					cmd.dpia_notify.payload.data.dpia_bw_alloc.allocated_bw;
					cmd.dpia_notify.payload.data.dpia_bw_alloc.allocated_bw;
			} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.est_bw_changed) {

			if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_failed)
				notify->result = DPIA_BW_REQ_FAILED;
			else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_request_succeeded)
				notify->result = DPIA_BW_REQ_SUCCESS;
			else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.est_bw_changed)
				notify->result = DPIA_EST_BW_CHANGED;
				notify->result = DPIA_EST_BW_CHANGED;
				notify->bw_alloc_reply.estimated_bw =
			else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_alloc_cap_changed)
						cmd.dpia_notify.payload.data.dpia_bw_alloc.estimated_bw;
			} else if (cmd.dpia_notify.payload.data.dpia_bw_alloc.bits.bw_alloc_cap_changed) {
				notify->result = DPIA_BW_ALLOC_CAPS_CHANGED;
				notify->result = DPIA_BW_ALLOC_CAPS_CHANGED;
		}
		}
		}
		break;
		break;
	default:
	default:
		notify->type = DMUB_NOTIFICATION_NO_DATA;
		notify->type = DMUB_NOTIFICATION_NO_DATA;