Loading drivers/gpu/drm/nouveau/nouveau_bios.c +4 −2 Original line number Diff line number Diff line Loading @@ -5834,7 +5834,8 @@ parse_dcb_gpio_table(struct nvbios *bios) e = new_gpio_entry(bios); e->tag = DCB_GPIO_TVDAC0; e->line = tvdac_gpio[1] >> 4; e->invert = tvdac_gpio[0] & 2; e->state[0] = !!(tvdac_gpio[0] & 2); e->state[1] = !e->state[0]; } goto no_table; Loading @@ -5858,7 +5859,8 @@ parse_dcb_gpio_table(struct nvbios *bios) } e->line = (e->entry & 0x001f); e->invert = ((e->entry & 0xf800) >> 11) != 4; e->state[0] = ((e->entry & 0xf800) >> 11) != 4; e->state[1] = !e->state[0]; } else { e->entry = ROM32(entry[0]); e->tag = (e->entry & 0x0000ff00) >> 8; Loading drivers/gpu/drm/nouveau/nouveau_bios.h +0 −1 Original line number Diff line number Diff line Loading @@ -65,7 +65,6 @@ enum dcb_gpio_tag { struct dcb_gpio_entry { enum dcb_gpio_tag tag; int line; bool invert; uint32_t entry; uint8_t state_default; uint8_t state[2]; Loading drivers/gpu/drm/nouveau/nv10_gpio.c +2 −2 Original line number Diff line number Diff line Loading @@ -68,7 +68,7 @@ nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag) value = NVReadCRTC(dev, 0, reg) >> shift; return (ent->invert ? 1 : 0) ^ (value & 1); return (value & 1) == ent->state[1]; } int Loading @@ -83,7 +83,7 @@ nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state) if (!get_gpio_location(ent, ®, &shift, &mask)) return -ENODEV; value = ((ent->invert ? 1 : 0) ^ (state ? 1 : 0)) << shift; value = ent->state[state & 1] << shift; mask = ~(mask << shift); NVWriteCRTC(dev, 0, reg, value | (NVReadCRTC(dev, 0, reg) & mask)); Loading Loading
drivers/gpu/drm/nouveau/nouveau_bios.c +4 −2 Original line number Diff line number Diff line Loading @@ -5834,7 +5834,8 @@ parse_dcb_gpio_table(struct nvbios *bios) e = new_gpio_entry(bios); e->tag = DCB_GPIO_TVDAC0; e->line = tvdac_gpio[1] >> 4; e->invert = tvdac_gpio[0] & 2; e->state[0] = !!(tvdac_gpio[0] & 2); e->state[1] = !e->state[0]; } goto no_table; Loading @@ -5858,7 +5859,8 @@ parse_dcb_gpio_table(struct nvbios *bios) } e->line = (e->entry & 0x001f); e->invert = ((e->entry & 0xf800) >> 11) != 4; e->state[0] = ((e->entry & 0xf800) >> 11) != 4; e->state[1] = !e->state[0]; } else { e->entry = ROM32(entry[0]); e->tag = (e->entry & 0x0000ff00) >> 8; Loading
drivers/gpu/drm/nouveau/nouveau_bios.h +0 −1 Original line number Diff line number Diff line Loading @@ -65,7 +65,6 @@ enum dcb_gpio_tag { struct dcb_gpio_entry { enum dcb_gpio_tag tag; int line; bool invert; uint32_t entry; uint8_t state_default; uint8_t state[2]; Loading
drivers/gpu/drm/nouveau/nv10_gpio.c +2 −2 Original line number Diff line number Diff line Loading @@ -68,7 +68,7 @@ nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag) value = NVReadCRTC(dev, 0, reg) >> shift; return (ent->invert ? 1 : 0) ^ (value & 1); return (value & 1) == ent->state[1]; } int Loading @@ -83,7 +83,7 @@ nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state) if (!get_gpio_location(ent, ®, &shift, &mask)) return -ENODEV; value = ((ent->invert ? 1 : 0) ^ (state ? 1 : 0)) << shift; value = ent->state[state & 1] << shift; mask = ~(mask << shift); NVWriteCRTC(dev, 0, reg, value | (NVReadCRTC(dev, 0, reg) & mask)); Loading