Loading include/dt-bindings/memory/tegra124-mc.h +68 −0 Original line number Diff line number Diff line Loading @@ -54,4 +54,72 @@ #define TEGRA124_MC_RESET_ISP2B 22 #define TEGRA124_MC_RESET_GPU 23 #define TEGRA124_MC_PTCR 0 #define TEGRA124_MC_DISPLAY0A 1 #define TEGRA124_MC_DISPLAY0AB 2 #define TEGRA124_MC_DISPLAY0B 3 #define TEGRA124_MC_DISPLAY0BB 4 #define TEGRA124_MC_DISPLAY0C 5 #define TEGRA124_MC_DISPLAY0CB 6 #define TEGRA124_MC_AFIR 14 #define TEGRA124_MC_AVPCARM7R 15 #define TEGRA124_MC_DISPLAYHC 16 #define TEGRA124_MC_DISPLAYHCB 17 #define TEGRA124_MC_HDAR 21 #define TEGRA124_MC_HOST1XDMAR 22 #define TEGRA124_MC_HOST1XR 23 #define TEGRA124_MC_MSENCSRD 28 #define TEGRA124_MC_PPCSAHBDMAR 29 #define TEGRA124_MC_PPCSAHBSLVR 30 #define TEGRA124_MC_SATAR 31 #define TEGRA124_MC_VDEBSEVR 34 #define TEGRA124_MC_VDEMBER 35 #define TEGRA124_MC_VDEMCER 36 #define TEGRA124_MC_VDETPER 37 #define TEGRA124_MC_MPCORELPR 38 #define TEGRA124_MC_MPCORER 39 #define TEGRA124_MC_MSENCSWR 43 #define TEGRA124_MC_AFIW 49 #define TEGRA124_MC_AVPCARM7W 50 #define TEGRA124_MC_HDAW 53 #define TEGRA124_MC_HOST1XW 54 #define TEGRA124_MC_MPCORELPW 56 #define TEGRA124_MC_MPCOREW 57 #define TEGRA124_MC_PPCSAHBDMAW 59 #define TEGRA124_MC_PPCSAHBSLVW 60 #define TEGRA124_MC_SATAW 61 #define TEGRA124_MC_VDEBSEVW 62 #define TEGRA124_MC_VDEDBGW 63 #define TEGRA124_MC_VDEMBEW 64 #define TEGRA124_MC_VDETPMW 65 #define TEGRA124_MC_ISPRA 68 #define TEGRA124_MC_ISPWA 70 #define TEGRA124_MC_ISPWB 71 #define TEGRA124_MC_XUSB_HOSTR 74 #define TEGRA124_MC_XUSB_HOSTW 75 #define TEGRA124_MC_XUSB_DEVR 76 #define TEGRA124_MC_XUSB_DEVW 77 #define TEGRA124_MC_ISPRAB 78 #define TEGRA124_MC_ISPWAB 80 #define TEGRA124_MC_ISPWBB 81 #define TEGRA124_MC_TSECSRD 84 #define TEGRA124_MC_TSECSWR 85 #define TEGRA124_MC_A9AVPSCR 86 #define TEGRA124_MC_A9AVPSCW 87 #define TEGRA124_MC_GPUSRD 88 #define TEGRA124_MC_GPUSWR 89 #define TEGRA124_MC_DISPLAYT 90 #define TEGRA124_MC_SDMMCRA 96 #define TEGRA124_MC_SDMMCRAA 97 #define TEGRA124_MC_SDMMCR 98 #define TEGRA124_MC_SDMMCRAB 99 #define TEGRA124_MC_SDMMCWA 100 #define TEGRA124_MC_SDMMCWAA 101 #define TEGRA124_MC_SDMMCW 102 #define TEGRA124_MC_SDMMCWAB 103 #define TEGRA124_MC_VICSRD 108 #define TEGRA124_MC_VICSWR 109 #define TEGRA124_MC_VIW 114 #define TEGRA124_MC_DISPLAYD 115 #endif include/dt-bindings/memory/tegra20-mc.h +53 −0 Original line number Diff line number Diff line Loading @@ -18,4 +18,57 @@ #define TEGRA20_MC_RESET_VDE 13 #define TEGRA20_MC_RESET_VI 14 #define TEGRA20_MC_DISPLAY0A 0 #define TEGRA20_MC_DISPLAY0AB 1 #define TEGRA20_MC_DISPLAY0B 2 #define TEGRA20_MC_DISPLAY0BB 3 #define TEGRA20_MC_DISPLAY0C 4 #define TEGRA20_MC_DISPLAY0CB 5 #define TEGRA20_MC_DISPLAY1B 6 #define TEGRA20_MC_DISPLAY1BB 7 #define TEGRA20_MC_EPPUP 8 #define TEGRA20_MC_G2PR 9 #define TEGRA20_MC_G2SR 10 #define TEGRA20_MC_MPEUNIFBR 11 #define TEGRA20_MC_VIRUV 12 #define TEGRA20_MC_AVPCARM7R 13 #define TEGRA20_MC_DISPLAYHC 14 #define TEGRA20_MC_DISPLAYHCB 15 #define TEGRA20_MC_FDCDRD 16 #define TEGRA20_MC_G2DR 17 #define TEGRA20_MC_HOST1XDMAR 18 #define TEGRA20_MC_HOST1XR 19 #define TEGRA20_MC_IDXSRD 20 #define TEGRA20_MC_MPCORER 21 #define TEGRA20_MC_MPE_IPRED 22 #define TEGRA20_MC_MPEAMEMRD 23 #define TEGRA20_MC_MPECSRD 24 #define TEGRA20_MC_PPCSAHBDMAR 25 #define TEGRA20_MC_PPCSAHBSLVR 26 #define TEGRA20_MC_TEXSRD 27 #define TEGRA20_MC_VDEBSEVR 28 #define TEGRA20_MC_VDEMBER 29 #define TEGRA20_MC_VDEMCER 30 #define TEGRA20_MC_VDETPER 31 #define TEGRA20_MC_EPPU 32 #define TEGRA20_MC_EPPV 33 #define TEGRA20_MC_EPPY 34 #define TEGRA20_MC_MPEUNIFBW 35 #define TEGRA20_MC_VIWSB 36 #define TEGRA20_MC_VIWU 37 #define TEGRA20_MC_VIWV 38 #define TEGRA20_MC_VIWY 39 #define TEGRA20_MC_G2DW 40 #define TEGRA20_MC_AVPCARM7W 41 #define TEGRA20_MC_FDCDWR 42 #define TEGRA20_MC_HOST1XW 43 #define TEGRA20_MC_ISPW 44 #define TEGRA20_MC_MPCOREW 45 #define TEGRA20_MC_MPECSWR 46 #define TEGRA20_MC_PPCSAHBDMAW 47 #define TEGRA20_MC_PPCSAHBSLVW 48 #define TEGRA20_MC_VDEBSEVW 49 #define TEGRA20_MC_VDEMBEW 50 #define TEGRA20_MC_VDETPMW 51 #endif include/dt-bindings/memory/tegra30-mc.h +67 −0 Original line number Diff line number Diff line Loading @@ -41,4 +41,71 @@ #define TEGRA30_MC_RESET_VDE 16 #define TEGRA30_MC_RESET_VI 17 #define TEGRA30_MC_PTCR 0 #define TEGRA30_MC_DISPLAY0A 1 #define TEGRA30_MC_DISPLAY0AB 2 #define TEGRA30_MC_DISPLAY0B 3 #define TEGRA30_MC_DISPLAY0BB 4 #define TEGRA30_MC_DISPLAY0C 5 #define TEGRA30_MC_DISPLAY0CB 6 #define TEGRA30_MC_DISPLAY1B 7 #define TEGRA30_MC_DISPLAY1BB 8 #define TEGRA30_MC_EPPUP 9 #define TEGRA30_MC_G2PR 10 #define TEGRA30_MC_G2SR 11 #define TEGRA30_MC_MPEUNIFBR 12 #define TEGRA30_MC_VIRUV 13 #define TEGRA30_MC_AFIR 14 #define TEGRA30_MC_AVPCARM7R 15 #define TEGRA30_MC_DISPLAYHC 16 #define TEGRA30_MC_DISPLAYHCB 17 #define TEGRA30_MC_FDCDRD 18 #define TEGRA30_MC_FDCDRD2 19 #define TEGRA30_MC_G2DR 20 #define TEGRA30_MC_HDAR 21 #define TEGRA30_MC_HOST1XDMAR 22 #define TEGRA30_MC_HOST1XR 23 #define TEGRA30_MC_IDXSRD 24 #define TEGRA30_MC_IDXSRD2 25 #define TEGRA30_MC_MPE_IPRED 26 #define TEGRA30_MC_MPEAMEMRD 27 #define TEGRA30_MC_MPECSRD 28 #define TEGRA30_MC_PPCSAHBDMAR 29 #define TEGRA30_MC_PPCSAHBSLVR 30 #define TEGRA30_MC_SATAR 31 #define TEGRA30_MC_TEXSRD 32 #define TEGRA30_MC_TEXSRD2 33 #define TEGRA30_MC_VDEBSEVR 34 #define TEGRA30_MC_VDEMBER 35 #define TEGRA30_MC_VDEMCER 36 #define TEGRA30_MC_VDETPER 37 #define TEGRA30_MC_MPCORELPR 38 #define TEGRA30_MC_MPCORER 39 #define TEGRA30_MC_EPPU 40 #define TEGRA30_MC_EPPV 41 #define TEGRA30_MC_EPPY 42 #define TEGRA30_MC_MPEUNIFBW 43 #define TEGRA30_MC_VIWSB 44 #define TEGRA30_MC_VIWU 45 #define TEGRA30_MC_VIWV 46 #define TEGRA30_MC_VIWY 47 #define TEGRA30_MC_G2DW 48 #define TEGRA30_MC_AFIW 49 #define TEGRA30_MC_AVPCARM7W 50 #define TEGRA30_MC_FDCDWR 51 #define TEGRA30_MC_FDCDWR2 52 #define TEGRA30_MC_HDAW 53 #define TEGRA30_MC_HOST1XW 54 #define TEGRA30_MC_ISPW 55 #define TEGRA30_MC_MPCORELPW 56 #define TEGRA30_MC_MPCOREW 57 #define TEGRA30_MC_MPECSWR 58 #define TEGRA30_MC_PPCSAHBDMAW 59 #define TEGRA30_MC_PPCSAHBSLVW 60 #define TEGRA30_MC_SATAW 61 #define TEGRA30_MC_VDEBSEVW 62 #define TEGRA30_MC_VDEDBGW 63 #define TEGRA30_MC_VDEMBEW 64 #define TEGRA30_MC_VDETPMW 65 #endif Loading
include/dt-bindings/memory/tegra124-mc.h +68 −0 Original line number Diff line number Diff line Loading @@ -54,4 +54,72 @@ #define TEGRA124_MC_RESET_ISP2B 22 #define TEGRA124_MC_RESET_GPU 23 #define TEGRA124_MC_PTCR 0 #define TEGRA124_MC_DISPLAY0A 1 #define TEGRA124_MC_DISPLAY0AB 2 #define TEGRA124_MC_DISPLAY0B 3 #define TEGRA124_MC_DISPLAY0BB 4 #define TEGRA124_MC_DISPLAY0C 5 #define TEGRA124_MC_DISPLAY0CB 6 #define TEGRA124_MC_AFIR 14 #define TEGRA124_MC_AVPCARM7R 15 #define TEGRA124_MC_DISPLAYHC 16 #define TEGRA124_MC_DISPLAYHCB 17 #define TEGRA124_MC_HDAR 21 #define TEGRA124_MC_HOST1XDMAR 22 #define TEGRA124_MC_HOST1XR 23 #define TEGRA124_MC_MSENCSRD 28 #define TEGRA124_MC_PPCSAHBDMAR 29 #define TEGRA124_MC_PPCSAHBSLVR 30 #define TEGRA124_MC_SATAR 31 #define TEGRA124_MC_VDEBSEVR 34 #define TEGRA124_MC_VDEMBER 35 #define TEGRA124_MC_VDEMCER 36 #define TEGRA124_MC_VDETPER 37 #define TEGRA124_MC_MPCORELPR 38 #define TEGRA124_MC_MPCORER 39 #define TEGRA124_MC_MSENCSWR 43 #define TEGRA124_MC_AFIW 49 #define TEGRA124_MC_AVPCARM7W 50 #define TEGRA124_MC_HDAW 53 #define TEGRA124_MC_HOST1XW 54 #define TEGRA124_MC_MPCORELPW 56 #define TEGRA124_MC_MPCOREW 57 #define TEGRA124_MC_PPCSAHBDMAW 59 #define TEGRA124_MC_PPCSAHBSLVW 60 #define TEGRA124_MC_SATAW 61 #define TEGRA124_MC_VDEBSEVW 62 #define TEGRA124_MC_VDEDBGW 63 #define TEGRA124_MC_VDEMBEW 64 #define TEGRA124_MC_VDETPMW 65 #define TEGRA124_MC_ISPRA 68 #define TEGRA124_MC_ISPWA 70 #define TEGRA124_MC_ISPWB 71 #define TEGRA124_MC_XUSB_HOSTR 74 #define TEGRA124_MC_XUSB_HOSTW 75 #define TEGRA124_MC_XUSB_DEVR 76 #define TEGRA124_MC_XUSB_DEVW 77 #define TEGRA124_MC_ISPRAB 78 #define TEGRA124_MC_ISPWAB 80 #define TEGRA124_MC_ISPWBB 81 #define TEGRA124_MC_TSECSRD 84 #define TEGRA124_MC_TSECSWR 85 #define TEGRA124_MC_A9AVPSCR 86 #define TEGRA124_MC_A9AVPSCW 87 #define TEGRA124_MC_GPUSRD 88 #define TEGRA124_MC_GPUSWR 89 #define TEGRA124_MC_DISPLAYT 90 #define TEGRA124_MC_SDMMCRA 96 #define TEGRA124_MC_SDMMCRAA 97 #define TEGRA124_MC_SDMMCR 98 #define TEGRA124_MC_SDMMCRAB 99 #define TEGRA124_MC_SDMMCWA 100 #define TEGRA124_MC_SDMMCWAA 101 #define TEGRA124_MC_SDMMCW 102 #define TEGRA124_MC_SDMMCWAB 103 #define TEGRA124_MC_VICSRD 108 #define TEGRA124_MC_VICSWR 109 #define TEGRA124_MC_VIW 114 #define TEGRA124_MC_DISPLAYD 115 #endif
include/dt-bindings/memory/tegra20-mc.h +53 −0 Original line number Diff line number Diff line Loading @@ -18,4 +18,57 @@ #define TEGRA20_MC_RESET_VDE 13 #define TEGRA20_MC_RESET_VI 14 #define TEGRA20_MC_DISPLAY0A 0 #define TEGRA20_MC_DISPLAY0AB 1 #define TEGRA20_MC_DISPLAY0B 2 #define TEGRA20_MC_DISPLAY0BB 3 #define TEGRA20_MC_DISPLAY0C 4 #define TEGRA20_MC_DISPLAY0CB 5 #define TEGRA20_MC_DISPLAY1B 6 #define TEGRA20_MC_DISPLAY1BB 7 #define TEGRA20_MC_EPPUP 8 #define TEGRA20_MC_G2PR 9 #define TEGRA20_MC_G2SR 10 #define TEGRA20_MC_MPEUNIFBR 11 #define TEGRA20_MC_VIRUV 12 #define TEGRA20_MC_AVPCARM7R 13 #define TEGRA20_MC_DISPLAYHC 14 #define TEGRA20_MC_DISPLAYHCB 15 #define TEGRA20_MC_FDCDRD 16 #define TEGRA20_MC_G2DR 17 #define TEGRA20_MC_HOST1XDMAR 18 #define TEGRA20_MC_HOST1XR 19 #define TEGRA20_MC_IDXSRD 20 #define TEGRA20_MC_MPCORER 21 #define TEGRA20_MC_MPE_IPRED 22 #define TEGRA20_MC_MPEAMEMRD 23 #define TEGRA20_MC_MPECSRD 24 #define TEGRA20_MC_PPCSAHBDMAR 25 #define TEGRA20_MC_PPCSAHBSLVR 26 #define TEGRA20_MC_TEXSRD 27 #define TEGRA20_MC_VDEBSEVR 28 #define TEGRA20_MC_VDEMBER 29 #define TEGRA20_MC_VDEMCER 30 #define TEGRA20_MC_VDETPER 31 #define TEGRA20_MC_EPPU 32 #define TEGRA20_MC_EPPV 33 #define TEGRA20_MC_EPPY 34 #define TEGRA20_MC_MPEUNIFBW 35 #define TEGRA20_MC_VIWSB 36 #define TEGRA20_MC_VIWU 37 #define TEGRA20_MC_VIWV 38 #define TEGRA20_MC_VIWY 39 #define TEGRA20_MC_G2DW 40 #define TEGRA20_MC_AVPCARM7W 41 #define TEGRA20_MC_FDCDWR 42 #define TEGRA20_MC_HOST1XW 43 #define TEGRA20_MC_ISPW 44 #define TEGRA20_MC_MPCOREW 45 #define TEGRA20_MC_MPECSWR 46 #define TEGRA20_MC_PPCSAHBDMAW 47 #define TEGRA20_MC_PPCSAHBSLVW 48 #define TEGRA20_MC_VDEBSEVW 49 #define TEGRA20_MC_VDEMBEW 50 #define TEGRA20_MC_VDETPMW 51 #endif
include/dt-bindings/memory/tegra30-mc.h +67 −0 Original line number Diff line number Diff line Loading @@ -41,4 +41,71 @@ #define TEGRA30_MC_RESET_VDE 16 #define TEGRA30_MC_RESET_VI 17 #define TEGRA30_MC_PTCR 0 #define TEGRA30_MC_DISPLAY0A 1 #define TEGRA30_MC_DISPLAY0AB 2 #define TEGRA30_MC_DISPLAY0B 3 #define TEGRA30_MC_DISPLAY0BB 4 #define TEGRA30_MC_DISPLAY0C 5 #define TEGRA30_MC_DISPLAY0CB 6 #define TEGRA30_MC_DISPLAY1B 7 #define TEGRA30_MC_DISPLAY1BB 8 #define TEGRA30_MC_EPPUP 9 #define TEGRA30_MC_G2PR 10 #define TEGRA30_MC_G2SR 11 #define TEGRA30_MC_MPEUNIFBR 12 #define TEGRA30_MC_VIRUV 13 #define TEGRA30_MC_AFIR 14 #define TEGRA30_MC_AVPCARM7R 15 #define TEGRA30_MC_DISPLAYHC 16 #define TEGRA30_MC_DISPLAYHCB 17 #define TEGRA30_MC_FDCDRD 18 #define TEGRA30_MC_FDCDRD2 19 #define TEGRA30_MC_G2DR 20 #define TEGRA30_MC_HDAR 21 #define TEGRA30_MC_HOST1XDMAR 22 #define TEGRA30_MC_HOST1XR 23 #define TEGRA30_MC_IDXSRD 24 #define TEGRA30_MC_IDXSRD2 25 #define TEGRA30_MC_MPE_IPRED 26 #define TEGRA30_MC_MPEAMEMRD 27 #define TEGRA30_MC_MPECSRD 28 #define TEGRA30_MC_PPCSAHBDMAR 29 #define TEGRA30_MC_PPCSAHBSLVR 30 #define TEGRA30_MC_SATAR 31 #define TEGRA30_MC_TEXSRD 32 #define TEGRA30_MC_TEXSRD2 33 #define TEGRA30_MC_VDEBSEVR 34 #define TEGRA30_MC_VDEMBER 35 #define TEGRA30_MC_VDEMCER 36 #define TEGRA30_MC_VDETPER 37 #define TEGRA30_MC_MPCORELPR 38 #define TEGRA30_MC_MPCORER 39 #define TEGRA30_MC_EPPU 40 #define TEGRA30_MC_EPPV 41 #define TEGRA30_MC_EPPY 42 #define TEGRA30_MC_MPEUNIFBW 43 #define TEGRA30_MC_VIWSB 44 #define TEGRA30_MC_VIWU 45 #define TEGRA30_MC_VIWV 46 #define TEGRA30_MC_VIWY 47 #define TEGRA30_MC_G2DW 48 #define TEGRA30_MC_AFIW 49 #define TEGRA30_MC_AVPCARM7W 50 #define TEGRA30_MC_FDCDWR 51 #define TEGRA30_MC_FDCDWR2 52 #define TEGRA30_MC_HDAW 53 #define TEGRA30_MC_HOST1XW 54 #define TEGRA30_MC_ISPW 55 #define TEGRA30_MC_MPCORELPW 56 #define TEGRA30_MC_MPCOREW 57 #define TEGRA30_MC_MPECSWR 58 #define TEGRA30_MC_PPCSAHBDMAW 59 #define TEGRA30_MC_PPCSAHBSLVW 60 #define TEGRA30_MC_SATAW 61 #define TEGRA30_MC_VDEBSEVW 62 #define TEGRA30_MC_VDEDBGW 63 #define TEGRA30_MC_VDEMBEW 64 #define TEGRA30_MC_VDETPMW 65 #endif