Commit 85b62ff2 authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Mauro Carvalho Chehab
Browse files

media: dt-bindings: media: nxp,imx7-mipi-csi2: Add i.MX8MM support 



The i.MX8MM integrates a newer version of the CSIS CSI-2 receiver as the
i.MX7 family. Differences in integration are are:

- An additional clock is required
- Up to 4 data lanes are supported
- No reset or PHY supply is present

Support it in the DT binding.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: default avatarRui Miguel Silva <rmfrfs@gmail.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
parent acdff8e1

Documentation/devicetree/bindings/media/nxp,imx7-mipi-csi2.yaml

+95 −14
Original line number Original line Diff line number Diff line
@@ -4,15 +4,17 @@ 
$id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#

$id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#





title: NXP i.MX7 MIPI CSI-2 receiver

title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver





maintainers:

maintainers:

  - Rui Miguel Silva <rmfrfs@gmail.com>

  - Rui Miguel Silva <rmfrfs@gmail.com>

  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>





description: |-

description: |-

  The NXP i.MX7 SoC family includes a MIPI CSI-2 receiver IP core, documented

  The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2

  as "CSIS V3.3". The IP core seems to originate from Samsung, and may be

  receiver IP core named CSIS. The IP core originates from Samsung, and may be

  compatible with some of the Exynos4 ad S5P SoCs.

  compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version

  3.3, and i.MX8 SoCs use CSIS version 3.6.3.





  While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is

  While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is

  completely wrapped by the CSIS and doesn't expose a control interface of its

  completely wrapped by the CSIS and doesn't expose a control interface of its
@@ -20,7 +22,9 @@ description: |- 




properties:

properties:

  compatible:

  compatible:

    const: fsl,imx7-mipi-csi2

    enum:

      - fsl,imx7-mipi-csi2

      - fsl,imx8mm-mipi-csi2





  reg:

  reg:

    maxItems: 1

    maxItems: 1
@@ -29,16 +33,20 @@ properties: 
    maxItems: 1

    maxItems: 1





  clocks:

  clocks:

    minItems: 3

    items:

    items:

      - description: The peripheral clock (a.k.a. APB clock)

      - description: The peripheral clock (a.k.a. APB clock)

      - description: The external clock (optionally used as the pixel clock)

      - description: The external clock (optionally used as the pixel clock)

      - description: The MIPI D-PHY clock

      - description: The MIPI D-PHY clock

      - description: The AXI clock





  clock-names:

  clock-names:

    minItems: 3

    items:

    items:

      - const: pclk

      - const: pclk

      - const: wrap

      - const: wrap

      - const: phy

      - const: phy

      - const: axi





  power-domains:

  power-domains:

    maxItems: 1

    maxItems: 1
@@ -71,16 +79,30 @@ properties: 




            properties:

            properties:

              data-lanes:

              data-lanes:

                oneOf:

                items:

                  - items:

                  minItems: 1

                      - const: 1

                  maxItems: 4

                  - items:

                  items:

                    - const: 1

                    - const: 1

                    - const: 2

                    - const: 2

                    - const: 3

                    - const: 4





            required:

            required:

              - data-lanes

              - data-lanes





            allOf:

              - if:

                  properties:

                    compatible:

                      contains:

                        const: fsl,imx7-mipi-csi2

                then:

                  properties:

                    data-lanes:

                      items:

                        maxItems: 2



      port@1:

      port@1:

        $ref: /schemas/graph.yaml#/properties/port

        $ref: /schemas/graph.yaml#/properties/port

        description:

        description:
@@ -93,12 +115,29 @@ required: 
  - clocks

  - clocks

  - clock-names

  - clock-names

  - power-domains

  - power-domains

  - phy-supply

  - resets

  - ports

  - ports





additionalProperties: false

additionalProperties: false





allOf:

  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx7-mipi-csi2

    then:

      required:

        - phy-supply

        - resets

    else:

      properties:

        clocks:

          minItems: 4

        clock-names:

          minItems: 4

        phy-supply: false

        resets: false



examples:

examples:

  - |

  - |

    #include <dt-bindings/clock/imx7d-clock.h>

    #include <dt-bindings/clock/imx7d-clock.h>
@@ -106,7 +145,7 @@ examples: 
    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/reset/imx7-reset.h>

    #include <dt-bindings/reset/imx7-reset.h>





    mipi_csi: mipi-csi@30750000 {

    mipi-csi@30750000 {

        compatible = "fsl,imx7-mipi-csi2";

        compatible = "fsl,imx7-mipi-csi2";

        reg = <0x30750000 0x10000>;

        reg = <0x30750000 0x10000>;

        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -144,4 +183,46 @@ examples: 
        };

        };

    };

    };





  - |

    #include <dt-bindings/clock/imx8mm-clock.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    mipi-csi@32e30000 {

        compatible = "fsl,imx8mm-mipi-csi2";

        reg = <0x32e30000 0x1000>;

        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;

        clock-frequency = <333000000>;

        clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,

                 <&clk IMX8MM_CLK_CSI1_ROOT>,

                 <&clk IMX8MM_CLK_CSI1_PHY_REF>,

                 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;

        clock-names = "pclk", "wrap", "phy", "axi";

        power-domains = <&mipi_pd>;



        status = "disabled";



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                reg = <0>;



                imx8mm_mipi_csi_in: endpoint {

                    remote-endpoint = <&imx477_out>;

                    data-lanes = <1 2 3 4>;

                };

            };



            port@1 {

                reg = <1>;



                imx8mm_mipi_csi_out: endpoint {

                    remote-endpoint = <&csi_in>;

                };

            };

        };

    };



...
 
...