Commit 85d31226 authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Simon Horman
Browse files

ARM: dts: r8a7745: Add CAN[01] SoC support 



Add the definitions for can0 and can1 to the SoC .dtsi.

Signed-off-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: default avatarBiju Das <biju.das@bp.renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 97b94d25

arch/arm/boot/dts/r8a7745.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -1049,6 +1049,34 @@ usb2: usb-channel@2 { 
				#phy-cells = <1>;

			};

		};



		can0: can@e6e80000 {

			compatible = "renesas,can-r8a7745",

				     "renesas,rcar-gen2-can";

			reg = <0 0xe6e80000 0 0x1000>;

			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 916>,

				 <&cpg CPG_CORE R8A7745_CLK_RCAN>,

				 <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;

			resets = <&cpg 916>;

			status = "disabled";

		};



		can1: can@e6e88000 {

			compatible = "renesas,can-r8a7745",

				     "renesas,rcar-gen2-can";

			reg = <0 0xe6e88000 0 0x1000>;

			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 915>,

				 <&cpg CPG_CORE R8A7745_CLK_RCAN>,

				 <&can_clk>;

			clock-names = "clkp1", "clkp2", "can_clk";

			power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;

			resets = <&cpg 915>;

			status = "disabled";

		};

	};



	/* External root clock */
@@ -1066,6 +1094,14 @@ usb_extal_clk: usb_extal { 
		clock-frequency = <48000000>;

	};



	/* External CAN clock */

	can_clk: can {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board. */

		clock-frequency = <0>;

	};



	/* External SCIF clock */

	scif_clk: scif {

		compatible = "fixed-clock";