cxl/Documentation: List attribute permissions (86677a4e) · Commits · jan.koester / Linux

Documentation/ABI/testing/sysfs-bus-cxl

+41 −40

Original line number	Original line	Diff line number	Diff line
	@@ -57,28 +57,28 @@ Date: June, 2021
	KernelVersion: v5.14		KernelVersion: v5.14
	Contact: linux-cxl@vger.kernel.org		Contact: linux-cxl@vger.kernel.org
	Description:		Description:
	CXL device objects export the devtype attribute which mirrors		(RO) CXL device objects export the devtype attribute which
	the same value communicated in the DEVTYPE environment variable		mirrors the same value communicated in the DEVTYPE environment
	for uevents for devices on the "cxl" bus.		variable for uevents for devices on the "cxl" bus.

	What: /sys/bus/cxl/devices/*/modalias		What: /sys/bus/cxl/devices/*/modalias
	Date: December, 2021		Date: December, 2021
	KernelVersion: v5.18		KernelVersion: v5.18
	Contact: linux-cxl@vger.kernel.org		Contact: linux-cxl@vger.kernel.org
	Description:		Description:
	CXL device objects export the modalias attribute which mirrors		(RO) CXL device objects export the modalias attribute which
	the same value communicated in the MODALIAS environment variable		mirrors the same value communicated in the MODALIAS environment
	for uevents for devices on the "cxl" bus.		variable for uevents for devices on the "cxl" bus.

	What: /sys/bus/cxl/devices/portX/uport		What: /sys/bus/cxl/devices/portX/uport
	Date: June, 2021		Date: June, 2021
	KernelVersion: v5.14		KernelVersion: v5.14
	Contact: linux-cxl@vger.kernel.org		Contact: linux-cxl@vger.kernel.org
	Description:		Description:
	CXL port objects are enumerated from either a platform firmware		(RO) CXL port objects are enumerated from either a platform
	device (ACPI0017 and ACPI0016) or PCIe switch upstream port with		firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
	CXL component registers. The 'uport' symlink connects the CXL		port with CXL component registers. The 'uport' symlink connects
	portX object to the device that published the CXL port		the CXL portX object to the device that published the CXL port
	capability.		capability.

	What: /sys/bus/cxl/devices/portX/dportY		What: /sys/bus/cxl/devices/portX/dportY
	@@ -86,20 +86,20 @@ Date: June, 2021
	KernelVersion: v5.14		KernelVersion: v5.14
	Contact: linux-cxl@vger.kernel.org		Contact: linux-cxl@vger.kernel.org
	Description:		Description:
	CXL port objects are enumerated from either a platform firmware		(RO) CXL port objects are enumerated from either a platform
	device (ACPI0017 and ACPI0016) or PCIe switch upstream port with		firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
	CXL component registers. The 'dportY' symlink identifies one or		port with CXL component registers. The 'dportY' symlink
	more downstream ports that the upstream port may target in its		identifies one or more downstream ports that the upstream port
	decode of CXL memory resources. The 'Y' integer reflects the		may target in its decode of CXL memory resources. The 'Y'
	hardware port unique-id used in the hardware decoder target		integer reflects the hardware port unique-id used in the
	list.		hardware decoder target list.

	What: /sys/bus/cxl/devices/decoderX.Y		What: /sys/bus/cxl/devices/decoderX.Y
	Date: June, 2021		Date: June, 2021
	KernelVersion: v5.14		KernelVersion: v5.14
	Contact: linux-cxl@vger.kernel.org		Contact: linux-cxl@vger.kernel.org
	Description:		Description:
	CXL decoder objects are enumerated from either a platform		(RO) CXL decoder objects are enumerated from either a platform
	firmware description, or a CXL HDM decoder register set in a		firmware description, or a CXL HDM decoder register set in a
	PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder		PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
	Capability Structure). The 'X' in decoderX.Y represents the		Capability Structure). The 'X' in decoderX.Y represents the
	@@ -111,42 +111,43 @@ Date: June, 2021
	KernelVersion: v5.14		KernelVersion: v5.14
	Contact: linux-cxl@vger.kernel.org		Contact: linux-cxl@vger.kernel.org
	Description:		Description:
	The 'start' and 'size' attributes together convey the physical		(RO) The 'start' and 'size' attributes together convey the
	address base and number of bytes mapped in the decoder's decode		physical address base and number of bytes mapped in the
	window. For decoders of devtype "cxl_decoder_root" the address		decoder's decode window. For decoders of devtype
	range is fixed. For decoders of devtype "cxl_decoder_switch" the		"cxl_decoder_root" the address range is fixed. For decoders of
	address is bounded by the decode range of the cxl_port ancestor		devtype "cxl_decoder_switch" the address is bounded by the
	of the decoder's cxl_port, and dynamically updates based on the		decode range of the cxl_port ancestor of the decoder's cxl_port,
	active memory regions in that address space.		and dynamically updates based on the active memory regions in
			that address space.

	What: /sys/bus/cxl/devices/decoderX.Y/locked		What: /sys/bus/cxl/devices/decoderX.Y/locked
	Date: June, 2021		Date: June, 2021
	KernelVersion: v5.14		KernelVersion: v5.14
	Contact: linux-cxl@vger.kernel.org		Contact: linux-cxl@vger.kernel.org
	Description:		Description:
	CXL HDM decoders have the capability to lock the configuration		(RO) CXL HDM decoders have the capability to lock the
	until the next device reset. For decoders of devtype		configuration until the next device reset. For decoders of
	"cxl_decoder_root" there is no standard facility to unlock them.		devtype "cxl_decoder_root" there is no standard facility to
	For decoders of devtype "cxl_decoder_switch" a secondary bus		unlock them. For decoders of devtype "cxl_decoder_switch" a
	reset, of the PCIe bridge that provides the bus for this		secondary bus reset, of the PCIe bridge that provides the bus
	decoders uport, unlocks / resets the decoder.		for this decoders uport, unlocks / resets the decoder.

	What: /sys/bus/cxl/devices/decoderX.Y/target_list		What: /sys/bus/cxl/devices/decoderX.Y/target_list
	Date: June, 2021		Date: June, 2021
	KernelVersion: v5.14		KernelVersion: v5.14
	Contact: linux-cxl@vger.kernel.org		Contact: linux-cxl@vger.kernel.org
	Description:		Description:
	Display a comma separated list of the current decoder target		(RO) Display a comma separated list of the current decoder
	configuration. The list is ordered by the current configured		target configuration. The list is ordered by the current
	interleave order of the decoder's dport instances. Each entry in		configured interleave order of the decoder's dport instances.
	the list is a dport id.		Each entry in the list is a dport id.

	What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}		What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
	Date: June, 2021		Date: June, 2021
	KernelVersion: v5.14		KernelVersion: v5.14
	Contact: linux-cxl@vger.kernel.org		Contact: linux-cxl@vger.kernel.org
	Description:		Description:
	When a CXL decoder is of devtype "cxl_decoder_root", it		(RO) When a CXL decoder is of devtype "cxl_decoder_root", it
	represents a fixed memory window identified by platform		represents a fixed memory window identified by platform
	firmware. A fixed window may only support a subset of memory		firmware. A fixed window may only support a subset of memory
	types. The 'cap_*' attributes indicate whether persistent		types. The 'cap_*' attributes indicate whether persistent
	@@ -158,8 +159,8 @@ Date: June, 2021
	KernelVersion: v5.14		KernelVersion: v5.14
	Contact: linux-cxl@vger.kernel.org		Contact: linux-cxl@vger.kernel.org
	Description:		Description:
	When a CXL decoder is of devtype "cxl_decoder_switch", it can		(RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
	optionally decode either accelerator memory (type-2) or expander		can optionally decode either accelerator memory (type-2) or
	memory (type-3). The 'target_type' attribute indicates the		expander memory (type-3). The 'target_type' attribute indicates
	current setting which may dynamically change based on what		the current setting which may dynamically change based on what
	memory regions are activated in this decode hierarchy.		memory regions are activated in this decode hierarchy.