Commit 86d2d921 authored by Robin Murphy's avatar Robin Murphy Committed by Will Deacon
Browse files

iommu/arm-smmu-v3: Remove the page 1 fixup 



Since we now keep track of page 1 via a separate pointer that already
encapsulates aliasing to page 0 as necessary, we can remove the clunky
fixup routine and simply use the relevant bases directly. The current
architecture spec (IHI0070D.a) defines SMMU_{EVENTQ,PRIQ}_{PROD,CONS} as
offsets relative to page 1, so the cleanup represents a little bit of
convergence as well as just lines of code saved.

Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/08d9bda570bb5681f11a2f250a31be9ef763b8c5.1611238182.git.robin.murphy@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent d8498b1e

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+16 −26
Original line number Diff line number Diff line
@@ -88,15 +88,6 @@ static struct arm_smmu_option_prop arm_smmu_options[] = { 
	{ 0, NULL},

};



static inline void __iomem *arm_smmu_page1_fixup(unsigned long offset,

						 struct arm_smmu_device *smmu)

{

	if (offset > SZ_64K)

		return smmu->page1 + offset - SZ_64K;



	return smmu->base + offset;

}



static void parse_driver_options(struct arm_smmu_device *smmu)

{

	int i = 0;
@@ -2611,6 +2602,7 @@ static struct iommu_ops arm_smmu_ops = { 
/* Probing and initialisation functions */

static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,

				   struct arm_smmu_queue *q,

				   void __iomem *page,

				   unsigned long prod_off,

				   unsigned long cons_off,

				   size_t dwords, const char *name)
@@ -2639,8 +2631,8 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, 
			 1 << q->llq.max_n_shift, name);

	}



	q->prod_reg	= arm_smmu_page1_fixup(prod_off, smmu);

	q->cons_reg	= arm_smmu_page1_fixup(cons_off, smmu);

	q->prod_reg	= page + prod_off;

	q->cons_reg	= page + cons_off;

	q->ent_dwords	= dwords;



	q->q_base  = Q_BASE_RWA;
@@ -2684,9 +2676,9 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) 
	int ret;



	/* cmdq */

	ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, ARM_SMMU_CMDQ_PROD,

				      ARM_SMMU_CMDQ_CONS, CMDQ_ENT_DWORDS,

				      "cmdq");

	ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base,

				      ARM_SMMU_CMDQ_PROD, ARM_SMMU_CMDQ_CONS,

				      CMDQ_ENT_DWORDS, "cmdq");

	if (ret)

		return ret;
@@ -2695,9 +2687,9 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) 
		return ret;



	/* evtq */

	ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, ARM_SMMU_EVTQ_PROD,

				      ARM_SMMU_EVTQ_CONS, EVTQ_ENT_DWORDS,

				      "evtq");

	ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1,

				      ARM_SMMU_EVTQ_PROD, ARM_SMMU_EVTQ_CONS,

				      EVTQ_ENT_DWORDS, "evtq");

	if (ret)

		return ret;
@@ -2705,9 +2697,9 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) 
	if (!(smmu->features & ARM_SMMU_FEAT_PRI))

		return 0;



	return arm_smmu_init_one_queue(smmu, &smmu->priq.q, ARM_SMMU_PRIQ_PROD,

				       ARM_SMMU_PRIQ_CONS, PRIQ_ENT_DWORDS,

				       "priq");

	return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1,

				       ARM_SMMU_PRIQ_PROD, ARM_SMMU_PRIQ_CONS,

				       PRIQ_ENT_DWORDS, "priq");

}



static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu)
@@ -3099,10 +3091,8 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) 


	/* Event queue */

	writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE);

	writel_relaxed(smmu->evtq.q.llq.prod,

		       arm_smmu_page1_fixup(ARM_SMMU_EVTQ_PROD, smmu));

	writel_relaxed(smmu->evtq.q.llq.cons,

		       arm_smmu_page1_fixup(ARM_SMMU_EVTQ_CONS, smmu));

	writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD);

	writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS);



	enables |= CR0_EVTQEN;

	ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
@@ -3117,9 +3107,9 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) 
		writeq_relaxed(smmu->priq.q.q_base,

			       smmu->base + ARM_SMMU_PRIQ_BASE);

		writel_relaxed(smmu->priq.q.llq.prod,

			       arm_smmu_page1_fixup(ARM_SMMU_PRIQ_PROD, smmu));

			       smmu->page1 + ARM_SMMU_PRIQ_PROD);

		writel_relaxed(smmu->priq.q.llq.cons,

			       arm_smmu_page1_fixup(ARM_SMMU_PRIQ_CONS, smmu));

			       smmu->page1 + ARM_SMMU_PRIQ_CONS);



		enables |= CR0_PRIQEN;

		ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

+4 −4
Original line number Diff line number Diff line
@@ -139,15 +139,15 @@ 
#define ARM_SMMU_CMDQ_CONS		0x9c



#define ARM_SMMU_EVTQ_BASE		0xa0

#define ARM_SMMU_EVTQ_PROD		0x100a8

#define ARM_SMMU_EVTQ_CONS		0x100ac

#define ARM_SMMU_EVTQ_PROD		0xa8

#define ARM_SMMU_EVTQ_CONS		0xac

#define ARM_SMMU_EVTQ_IRQ_CFG0		0xb0

#define ARM_SMMU_EVTQ_IRQ_CFG1		0xb8

#define ARM_SMMU_EVTQ_IRQ_CFG2		0xbc



#define ARM_SMMU_PRIQ_BASE		0xc0

#define ARM_SMMU_PRIQ_PROD		0x100c8

#define ARM_SMMU_PRIQ_CONS		0x100cc

#define ARM_SMMU_PRIQ_PROD		0xc8

#define ARM_SMMU_PRIQ_CONS		0xcc

#define ARM_SMMU_PRIQ_IRQ_CFG0		0xd0

#define ARM_SMMU_PRIQ_IRQ_CFG1		0xd8

#define ARM_SMMU_PRIQ_IRQ_CFG2		0xdc