Commit 876e835e authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: restyle dcn31 resource header inline with other asics



Style change for better consistency across codebase

Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Acked-by: default avatarAgustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent af9775a3
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+2 −2
Original line number Diff line number Diff line
@@ -1834,7 +1834,7 @@ static int dcn31_populate_dml_pipes_from_context(
	return pipe_cnt;
}

static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
{
	if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
@@ -1978,7 +1978,7 @@ static void dcn31_calculate_wm_and_dlg_fp(
	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
}

static void dcn31_calculate_wm_and_dlg(
void dcn31_calculate_wm_and_dlg(
		struct dc *dc, struct dc_state *context,
		display_e2e_pipe_params_st *pipes,
		int pipe_cnt,
+10 −0
Original line number Diff line number Diff line
@@ -35,6 +35,16 @@ struct dcn31_resource_pool {
	struct resource_pool base;
};

bool dcn31_validate_bandwidth(struct dc *dc,
		struct dc_state *context,
		bool fast_validate);
void dcn31_calculate_wm_and_dlg(
		struct dc *dc, struct dc_state *context,
		display_e2e_pipe_params_st *pipes,
		int pipe_cnt,
		int vlevel);
void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);

struct resource_pool *dcn31_create_resource_pool(
		const struct dc_init_data *init_data,
		struct dc *dc);