Commit 8779b88c authored by Jonathan Cameron's avatar Jonathan Cameron
Browse files

iio: dac: ad5064: Fix alignment for DMA safety 



____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 6a17a076 ("iio:dac:ad5064: Add support for the ad5629r and ad5669r")
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: default avatarNuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-44-jic23@kernel.org
parent 314d2b19

drivers/iio/dac/ad5064.c

+2 −2
Original line number Diff line number Diff line
@@ -115,13 +115,13 @@ struct ad5064_state { 
	struct mutex lock;



	/*

	 * DMA (thus cache coherency maintenance) requires the

	 * DMA (thus cache coherency maintenance) may require the

	 * transfer buffers to live in their own cache lines.

	 */

	union {

		u8 i2c[3];

		__be32 spi;

	} data ____cacheline_aligned;

	} data __aligned(IIO_DMA_MINALIGN);

};



enum ad5064_type {