Commit 88893986 authored Dec 21, 2020 by Sowjanya Komatineni Committed by Thierry Reding Jan 27, 2021

dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM



Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.

This patch adds clock ID for this to dt-binding.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

parent 5c8fe583

include/dt-bindings/clock/tegra210-car.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -307,7 +307,7 @@
		#define TEGRA210_CLK_AUDIO4 275
		#define TEGRA210_CLK_SPDIF 276
		/* 277 */
		/* 278 */
		#define TEGRA210_CLK_QSPI_PM 278
		/* 279 */
		/* 280 */
		#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */