Loading drivers/block/cciss.c +21 −2 Original line number Diff line number Diff line Loading @@ -582,12 +582,32 @@ static u32 unresettable_controller[] = { 0x3215103C, /* Smart Array E200i */ 0x3237103C, /* Smart Array E500 */ 0x323D103C, /* Smart Array P700m */ 0x40800E11, /* Smart Array 5i */ 0x409C0E11, /* Smart Array 6400 */ 0x409D0E11, /* Smart Array 6400 EM */ 0x40700E11, /* Smart Array 5300 */ 0x40820E11, /* Smart Array 532 */ 0x40830E11, /* Smart Array 5312 */ 0x409A0E11, /* Smart Array 641 */ 0x409B0E11, /* Smart Array 642 */ 0x40910E11, /* Smart Array 6i */ }; /* List of controllers which cannot even be soft reset */ static u32 soft_unresettable_controller[] = { 0x40800E11, /* Smart Array 5i */ 0x40700E11, /* Smart Array 5300 */ 0x40820E11, /* Smart Array 532 */ 0x40830E11, /* Smart Array 5312 */ 0x409A0E11, /* Smart Array 641 */ 0x409B0E11, /* Smart Array 642 */ 0x40910E11, /* Smart Array 6i */ /* Exclude 640x boards. These are two pci devices in one slot * which share a battery backed cache module. One controls the * cache, the other accesses the cache through the one that controls * it. If we reset the one controlling the cache, the other will * likely not be happy. Just forbid resetting this conjoined mess. */ 0x409C0E11, /* Smart Array 6400 */ 0x409D0E11, /* Smart Array 6400 EM */ }; Loading Loading @@ -4663,8 +4683,7 @@ static int cciss_kdump_hard_reset_controller(struct pci_dev *pdev) */ cciss_lookup_board_id(pdev, &board_id); if (!ctlr_is_resettable(board_id)) { dev_warn(&pdev->dev, "Cannot reset Smart Array 640x " "due to shared cache module."); dev_warn(&pdev->dev, "Controller not resettable\n"); return -ENODEV; } Loading Loading
drivers/block/cciss.c +21 −2 Original line number Diff line number Diff line Loading @@ -582,12 +582,32 @@ static u32 unresettable_controller[] = { 0x3215103C, /* Smart Array E200i */ 0x3237103C, /* Smart Array E500 */ 0x323D103C, /* Smart Array P700m */ 0x40800E11, /* Smart Array 5i */ 0x409C0E11, /* Smart Array 6400 */ 0x409D0E11, /* Smart Array 6400 EM */ 0x40700E11, /* Smart Array 5300 */ 0x40820E11, /* Smart Array 532 */ 0x40830E11, /* Smart Array 5312 */ 0x409A0E11, /* Smart Array 641 */ 0x409B0E11, /* Smart Array 642 */ 0x40910E11, /* Smart Array 6i */ }; /* List of controllers which cannot even be soft reset */ static u32 soft_unresettable_controller[] = { 0x40800E11, /* Smart Array 5i */ 0x40700E11, /* Smart Array 5300 */ 0x40820E11, /* Smart Array 532 */ 0x40830E11, /* Smart Array 5312 */ 0x409A0E11, /* Smart Array 641 */ 0x409B0E11, /* Smart Array 642 */ 0x40910E11, /* Smart Array 6i */ /* Exclude 640x boards. These are two pci devices in one slot * which share a battery backed cache module. One controls the * cache, the other accesses the cache through the one that controls * it. If we reset the one controlling the cache, the other will * likely not be happy. Just forbid resetting this conjoined mess. */ 0x409C0E11, /* Smart Array 6400 */ 0x409D0E11, /* Smart Array 6400 EM */ }; Loading Loading @@ -4663,8 +4683,7 @@ static int cciss_kdump_hard_reset_controller(struct pci_dev *pdev) */ cciss_lookup_board_id(pdev, &board_id); if (!ctlr_is_resettable(board_id)) { dev_warn(&pdev->dev, "Cannot reset Smart Array 640x " "due to shared cache module."); dev_warn(&pdev->dev, "Controller not resettable\n"); return -ENODEV; } Loading