Commit 8a5d8245 authored by Tony Cheng's avatar Tony Cheng Committed by Alex Deucher
Browse files

drm/amd/display: use some sensible time out 



40s time out is not sensible.

also make all udelay poll happen more frequently since CPU is busy anyways

Signed-off-by: default avatarTony Cheng <tony.cheng@amd.com>
Reviewed-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5aa72db7

drivers/gpu/drm/amd/display/dc/dc_helper.c

+5 −1
Original line number Diff line number Diff line
@@ -135,6 +135,9 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, 
	uint32_t reg_val;

	int i;



	/* something is terribly wrong if time out is > 200ms. (5Hz) */

	ASSERT(delay_between_poll_us * time_out_num_tries <= 200000);



	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {

		/* 35 seconds */

		delay_between_poll_us = 35000;
@@ -158,7 +161,8 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, 
	}



	dm_error("REG_WAIT timeout %dus * %d tries - %s line:%d\n",

			delay_between_poll_us, time_out_num_tries, func_name, line);

			delay_between_poll_us, time_out_num_tries,

			func_name, line);



	if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))

		BREAK_TO_DEBUGGER();

drivers/gpu/drm/amd/display/dc/dce/dce_abm.c

+6 −5
Original line number Diff line number Diff line
@@ -195,8 +195,9 @@ static void driver_set_backlight_level(struct dce_abm *abm_dce, uint32_t level) 
			BL_PWM_GRP1_REG_LOCK, 0);



	/* 5.4.4 Wait for pending bit to be cleared */

	REG_WAIT(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING,

			0, 10, 1000);

	REG_WAIT(BL_PWM_GRP1_REG_LOCK,

			BL_PWM_GRP1_REG_UPDATE_PENDING, 0,

			1, 10000);

}



static void dmcu_set_backlight_level(
@@ -224,7 +225,7 @@ static void dmcu_set_backlight_level( 


	/* waitDMCUReadyForCmd */

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT,

			0, 100, 800);

			0, 1, 80000);



	/* setDMCUParam_BL */

	REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, backlight_17_bit);
@@ -304,7 +305,7 @@ static bool dce_abm_set_level(struct abm *abm, uint32_t level) 
	struct dce_abm *abm_dce = TO_DCE_ABM(abm);



	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

			100, 800);

			1, 80000);



	/* setDMCUParam_ABMLevel */

	REG_UPDATE_2(MASTER_COMM_CMD_REG,
@@ -322,7 +323,7 @@ static bool dce_abm_immediate_disable(struct abm *abm) 
	struct dce_abm *abm_dce = TO_DCE_ABM(abm);



	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

			100, 800);

			1, 80000);



	/* setDMCUParam_ABMLevel */

	REG_UPDATE_2(MASTER_COMM_CMD_REG,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

+2 −2
Original line number Diff line number Diff line
@@ -262,7 +262,7 @@ static void dce_psr_wait_loop( 
	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;



	/* waitDMCUReadyForCmd */

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100);

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);



	masterCmdData1.u32 = 0;

	masterCmdData1.bits.wait_loop = wait_loop_number;
@@ -502,7 +502,7 @@ static void dcn10_psr_wait_loop( 
	union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;



	/* waitDMCUReadyForCmd */

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 100, 100);

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, 1, 10000);



	masterCmdData1.u32 = 0;

	masterCmdData1.bits.wait_loop = wait_loop_number;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+18 −9
Original line number Diff line number Diff line
@@ -264,28 +264,32 @@ static void dpp_pg_control( 
				DOMAIN1_POWER_GATE, power_gate);



		REG_WAIT(DOMAIN1_PG_STATUS,

				DOMAIN1_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);

				DOMAIN1_PGFSM_PWR_STATUS, pwr_status,

				1, 1000);

		break;

	case 1: /* DPP1 */

		REG_UPDATE(DOMAIN3_PG_CONFIG,

				DOMAIN3_POWER_GATE, power_gate);



		REG_WAIT(DOMAIN3_PG_STATUS,

				DOMAIN3_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);

				DOMAIN3_PGFSM_PWR_STATUS, pwr_status,

				1, 1000);

		break;

	case 2: /* DPP2 */

		REG_UPDATE(DOMAIN5_PG_CONFIG,

				DOMAIN5_POWER_GATE, power_gate);



		REG_WAIT(DOMAIN5_PG_STATUS,

				DOMAIN5_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);

				DOMAIN5_PGFSM_PWR_STATUS, pwr_status,

				1, 1000);

		break;

	case 3: /* DPP3 */

		REG_UPDATE(DOMAIN7_PG_CONFIG,

				DOMAIN7_POWER_GATE, power_gate);



		REG_WAIT(DOMAIN7_PG_STATUS,

				DOMAIN7_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);

				DOMAIN7_PGFSM_PWR_STATUS, pwr_status,

				1, 1000);

		break;

	default:

		BREAK_TO_DEBUGGER();
@@ -612,28 +616,32 @@ static void hubp_pg_control( 
				DOMAIN0_POWER_GATE, power_gate);



		REG_WAIT(DOMAIN0_PG_STATUS,

				DOMAIN0_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);

				DOMAIN0_PGFSM_PWR_STATUS, pwr_status,

				1, 1000);

		break;

	case 1: /* DCHUBP1 */

		REG_UPDATE(DOMAIN2_PG_CONFIG,

				DOMAIN2_POWER_GATE, power_gate);



		REG_WAIT(DOMAIN2_PG_STATUS,

				DOMAIN2_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);

				DOMAIN2_PGFSM_PWR_STATUS, pwr_status,

				1, 1000);

		break;

	case 2: /* DCHUBP2 */

		REG_UPDATE(DOMAIN4_PG_CONFIG,

				DOMAIN4_POWER_GATE, power_gate);



		REG_WAIT(DOMAIN4_PG_STATUS,

				DOMAIN4_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);

				DOMAIN4_PGFSM_PWR_STATUS, pwr_status,

				1, 1000);

		break;

	case 3: /* DCHUBP3 */

		REG_UPDATE(DOMAIN6_PG_CONFIG,

				DOMAIN6_POWER_GATE, power_gate);



		REG_WAIT(DOMAIN6_PG_STATUS,

				DOMAIN6_PGFSM_PWR_STATUS, pwr_status, 20000, 200000);

				DOMAIN6_PGFSM_PWR_STATUS, pwr_status,

				1, 1000);

		break;

	default:

		BREAK_TO_DEBUGGER();
@@ -1011,7 +1019,8 @@ static void reset_front_end( 


	if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)

		REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],

				VUPDATE_NO_LOCK_EVENT_OCCURRED, 1, 20000, 200000);

				VUPDATE_NO_LOCK_EVENT_OCCURRED, 1,

				1, 100000);



	plane_atomic_disable(dc, fe_idx);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c

+1 −1
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ static void mpc10_assert_idle_mpcc(struct mpc *mpc, int id) 
	ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));

	REG_WAIT(MPCC_STATUS[id],

			MPCC_IDLE, 1,

			1000, 1000);

			1, 100000);

}



static int mpc10_get_idle_mpcc_id(struct dcn10_mpc *mpc10)