Commit 8abe5e77 authored by Shawn Guo's avatar Shawn Guo Committed by Vinod Koul
Browse files

phy: qcom-qmp: Add QCM2290 USB3 PHY support 



Enable QCM2290 USB3 PHY support by adding the qmp_phy_cfg data which are
taken from downstream kernel.

Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210927064829.5752-3-shawn.guo@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 0b7c7ebe

drivers/phy/qualcomm/phy-qcom-qmp.c

+143 −0
Original line number Diff line number Diff line
@@ -135,6 +135,8 @@ enum qphy_reg_layout { 
	QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,

	QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,

	QPHY_PCS_POWER_DOWN_CONTROL,

	/* PCS_MISC registers */

	QPHY_PCS_MISC_TYPEC_CTRL,

	/* Keep last to ensure regs_layout arrays are properly initialized */

	QPHY_LAYOUT_SIZE

};
@@ -229,6 +231,16 @@ static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,

};



static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {

	[QPHY_SW_RESET]			= 0x00,

	[QPHY_PCS_POWER_DOWN_CONTROL]	= 0x04,

	[QPHY_START_CTRL]		= 0x08,

	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= 0xd8,

	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,

	[QPHY_PCS_STATUS]		= 0x174,

	[QPHY_PCS_MISC_TYPEC_CTRL]	= 0x00,

};



static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {

	[QPHY_START_CTRL]		= 0x00,

	[QPHY_PCS_READY_STATUS]		= 0x160,
@@ -2761,6 +2773,99 @@ static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),

};



static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),

	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),

};



static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),

};



static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),

};



static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),

};



struct qmp_phy;



/* struct qmp_phy_cfg - per-PHY initialization config */
@@ -2995,6 +3100,10 @@ static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { 
	"aux", "cfg_ahb", "ref"

};



static const char * const qcm2290_usb3phy_clk_l[] = {

	"cfg_ahb", "ref", "com_aux",

};



/* list of resets */

static const char * const msm8996_pciephy_reset_l[] = {

	"phy", "common", "cfg",
@@ -3008,6 +3117,10 @@ static const char * const sc7180_usb3phy_reset_l[] = { 
	"phy",

};



static const char * const qcm2290_usb3phy_reset_l[] = {

	"phy_phy", "phy",

};



static const char * const sdm845_pciephy_reset_l[] = {

	"phy",

};
@@ -3974,6 +4087,33 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { 
	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,

};



static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {

	.type			= PHY_TYPE_USB3,

	.nlanes			= 1,



	.serdes_tbl		= qcm2290_usb3_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(qcm2290_usb3_serdes_tbl),

	.tx_tbl			= qcm2290_usb3_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(qcm2290_usb3_tx_tbl),

	.rx_tbl			= qcm2290_usb3_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(qcm2290_usb3_rx_tbl),

	.pcs_tbl		= qcm2290_usb3_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(qcm2290_usb3_pcs_tbl),

	.clk_list		= qcm2290_usb3phy_clk_l,

	.num_clks		= ARRAY_SIZE(qcm2290_usb3phy_clk_l),

	.reset_list		= qcm2290_usb3phy_reset_l,

	.num_resets		= ARRAY_SIZE(qcm2290_usb3phy_reset_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= qcm2290_usb3phy_regs_layout,



	.start_ctrl		= SERDES_START | PCS_START,

	.pwrdn_ctrl		= SW_PWRDN,

	.phy_status		= PHYSTATUS,



	.is_dual_lane_phy	= true,

};



static void qcom_qmp_phy_configure_lane(void __iomem *base,

					const unsigned int *regs,

					const struct qmp_phy_init_tbl tbl[],
@@ -5605,6 +5745,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { 
	}, {

		.compatible = "qcom,sm8350-qmp-usb3-uni-phy",

		.data = &sm8350_usb3_uniphy_cfg,

	}, {

		.compatible = "qcom,qcm2290-qmp-usb3-phy",

		.data = &qcm2290_usb3phy_cfg,

	},

	{ },

};

drivers/phy/qualcomm/phy-qcom-qmp.h

+2 −0
Original line number Diff line number Diff line
@@ -169,6 +169,7 @@ 
#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM			0x0a8

#define QSERDES_COM_SYSCLK_EN_SEL			0x0ac

#define QSERDES_COM_RESETSM_CNTRL			0x0b4

#define QSERDES_COM_RESETSM_CNTRL2			0x0b8

#define QSERDES_COM_RESTRIM_CTRL			0x0bc

#define QSERDES_COM_RESCODE_DIV_NUM			0x0c4

#define QSERDES_COM_LOCK_CMP_EN				0x0c8
@@ -181,6 +182,7 @@ 
#define QSERDES_COM_DIV_FRAC_START1_MODE1		0x0e8

#define QSERDES_COM_DIV_FRAC_START2_MODE1		0x0ec

#define QSERDES_COM_DIV_FRAC_START3_MODE1		0x0f0

#define QSERDES_COM_INTEGLOOP_INITVAL			0x100

#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0		0x108

#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0		0x10c

#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1		0x110