serial: ucc_uart: replace ppc-specific IO accessors (8b1cdc40) · Commits · jan.koester / Linux

drivers/tty/serial/ucc_uart.c

+102 −108

Original line number	Original line	Diff line number	Diff line
	@@ -258,11 +258,11 @@ static unsigned int qe_uart_tx_empty(struct uart_port *port)
	struct qe_bd *bdp = qe_port->tx_bd_base;		struct qe_bd *bdp = qe_port->tx_bd_base;

	while (1) {		while (1) {
	if (in_be16(&bdp->status) & BD_SC_READY)		if (qe_ioread16be(&bdp->status) & BD_SC_READY)
	/* This BD is not done, so return "not done" */		/* This BD is not done, so return "not done" */
	return 0;		return 0;

	if (in_be16(&bdp->status) & BD_SC_WRAP)		if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
	/*		/*
	* This BD is done and it's the last one, so return		* This BD is done and it's the last one, so return
	* "done"		* "done"
	@@ -308,7 +308,7 @@ static void qe_uart_stop_tx(struct uart_port *port)
	struct uart_qe_port *qe_port =		struct uart_qe_port *qe_port =
	container_of(port, struct uart_qe_port, port);		container_of(port, struct uart_qe_port, port);

	clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);		qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
	}		}

	/*		/*
	@@ -343,10 +343,10 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
	p = qe2cpu_addr(bdp->buf, qe_port);		p = qe2cpu_addr(bdp->buf, qe_port);

	*p++ = port->x_char;		*p++ = port->x_char;
	out_be16(&bdp->length, 1);		qe_iowrite16be(1, &bdp->length);
	setbits16(&bdp->status, BD_SC_READY);		qe_setbits_be16(&bdp->status, BD_SC_READY);
	/* Get next BD. */		/* Get next BD. */
	if (in_be16(&bdp->status) & BD_SC_WRAP)		if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
	bdp = qe_port->tx_bd_base;		bdp = qe_port->tx_bd_base;
	else		else
	bdp++;		bdp++;
	@@ -365,7 +365,7 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
	/* Pick next descriptor and fill from buffer */		/* Pick next descriptor and fill from buffer */
	bdp = qe_port->tx_cur;		bdp = qe_port->tx_cur;

	while (!(in_be16(&bdp->status) & BD_SC_READY) &&		while (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&
	(xmit->tail != xmit->head)) {		(xmit->tail != xmit->head)) {
	count = 0;		count = 0;
	p = qe2cpu_addr(bdp->buf, qe_port);		p = qe2cpu_addr(bdp->buf, qe_port);
	@@ -378,11 +378,11 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
	break;		break;
	}		}

	out_be16(&bdp->length, count);		qe_iowrite16be(count, &bdp->length);
	setbits16(&bdp->status, BD_SC_READY);		qe_setbits_be16(&bdp->status, BD_SC_READY);

	/* Get next BD. */		/* Get next BD. */
	if (in_be16(&bdp->status) & BD_SC_WRAP)		if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
	bdp = qe_port->tx_bd_base;		bdp = qe_port->tx_bd_base;
	else		else
	bdp++;		bdp++;
	@@ -415,12 +415,12 @@ static void qe_uart_start_tx(struct uart_port *port)
	container_of(port, struct uart_qe_port, port);		container_of(port, struct uart_qe_port, port);

	/* If we currently are transmitting, then just return */		/* If we currently are transmitting, then just return */
	if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)		if (qe_ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
	return;		return;

	/* Otherwise, pump the port and start transmission */		/* Otherwise, pump the port and start transmission */
	if (qe_uart_tx_pump(qe_port))		if (qe_uart_tx_pump(qe_port))
	setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);		qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
	}		}

	/*		/*
	@@ -431,7 +431,7 @@ static void qe_uart_stop_rx(struct uart_port *port)
	struct uart_qe_port *qe_port =		struct uart_qe_port *qe_port =
	container_of(port, struct uart_qe_port, port);		container_of(port, struct uart_qe_port, port);

	clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);		qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
	}		}

	/* Start or stop sending break signal		/* Start or stop sending break signal
	@@ -470,14 +470,14 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)
	*/		*/
	bdp = qe_port->rx_cur;		bdp = qe_port->rx_cur;
	while (1) {		while (1) {
	status = in_be16(&bdp->status);		status = qe_ioread16be(&bdp->status);

	/* If this one is empty, then we assume we've read them all */		/* If this one is empty, then we assume we've read them all */
	if (status & BD_SC_EMPTY)		if (status & BD_SC_EMPTY)
	break;		break;

	/* get number of characters, and check space in RX buffer */		/* get number of characters, and check space in RX buffer */
	i = in_be16(&bdp->length);		i = qe_ioread16be(&bdp->length);

	/* If we don't have enough room in RX buffer for the entire BD,		/* If we don't have enough room in RX buffer for the entire BD,
	* then we try later, which will be the next RX interrupt.		* then we try later, which will be the next RX interrupt.
	@@ -508,9 +508,10 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)
	}		}

	/* This BD is ready to be used again. Clear status. get next */		/* This BD is ready to be used again. Clear status. get next */
	clrsetbits_be16(&bdp->status, BD_SC_BR \| BD_SC_FR \| BD_SC_PR \|		qe_clrsetbits_be16(&bdp->status,
	BD_SC_OV \| BD_SC_ID, BD_SC_EMPTY);		BD_SC_BR \| BD_SC_FR \| BD_SC_PR \| BD_SC_OV \| BD_SC_ID,
	if (in_be16(&bdp->status) & BD_SC_WRAP)		BD_SC_EMPTY);
			if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
	bdp = qe_port->rx_bd_base;		bdp = qe_port->rx_bd_base;
	else		else
	bdp++;		bdp++;
	@@ -569,8 +570,8 @@ static irqreturn_t qe_uart_int(int irq, void *data)
	u16 events;		u16 events;

	/* Clear the interrupts */		/* Clear the interrupts */
	events = in_be16(&uccp->ucce);		events = qe_ioread16be(&uccp->ucce);
	out_be16(&uccp->ucce, events);		qe_iowrite16be(events, &uccp->ucce);

	if (events & UCC_UART_UCCE_BRKE)		if (events & UCC_UART_UCCE_BRKE)
	uart_handle_break(&qe_port->port);		uart_handle_break(&qe_port->port);
	@@ -601,17 +602,17 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
	bdp = qe_port->rx_bd_base;		bdp = qe_port->rx_bd_base;
	qe_port->rx_cur = qe_port->rx_bd_base;		qe_port->rx_cur = qe_port->rx_bd_base;
	for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {		for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
	out_be16(&bdp->status, BD_SC_EMPTY \| BD_SC_INTRPT);		qe_iowrite16be(BD_SC_EMPTY \| BD_SC_INTRPT, &bdp->status);
	out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));		qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
	out_be16(&bdp->length, 0);		qe_iowrite16be(0, &bdp->length);
	bd_virt += qe_port->rx_fifosize;		bd_virt += qe_port->rx_fifosize;
	bdp++;		bdp++;
	}		}

	/* */		/* */
	out_be16(&bdp->status, BD_SC_WRAP \| BD_SC_EMPTY \| BD_SC_INTRPT);		qe_iowrite16be(BD_SC_WRAP \| BD_SC_EMPTY \| BD_SC_INTRPT, &bdp->status);
	out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));		qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
	out_be16(&bdp->length, 0);		qe_iowrite16be(0, &bdp->length);

	/* Set the physical address of the host memory		/* Set the physical address of the host memory
	* buffers in the buffer descriptors, and the		* buffers in the buffer descriptors, and the
	@@ -622,21 +623,21 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
	qe_port->tx_cur = qe_port->tx_bd_base;		qe_port->tx_cur = qe_port->tx_bd_base;
	bdp = qe_port->tx_bd_base;		bdp = qe_port->tx_bd_base;
	for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {		for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
	out_be16(&bdp->status, BD_SC_INTRPT);		qe_iowrite16be(BD_SC_INTRPT, &bdp->status);
	out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));		qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
	out_be16(&bdp->length, 0);		qe_iowrite16be(0, &bdp->length);
	bd_virt += qe_port->tx_fifosize;		bd_virt += qe_port->tx_fifosize;
	bdp++;		bdp++;
	}		}

	/* Loopback requires the preamble bit to be set on the first TX BD */		/* Loopback requires the preamble bit to be set on the first TX BD */
	#ifdef LOOPBACK		#ifdef LOOPBACK
	setbits16(&qe_port->tx_cur->status, BD_SC_P);		qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
	#endif		#endif

	out_be16(&bdp->status, BD_SC_WRAP \| BD_SC_INTRPT);		qe_iowrite16be(BD_SC_WRAP \| BD_SC_INTRPT, &bdp->status);
	out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));		qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
	out_be16(&bdp->length, 0);		qe_iowrite16be(0, &bdp->length);
	}		}

	/*		/*
	@@ -658,78 +659,74 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);		ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);

	/* Program the UCC UART parameter RAM */		/* Program the UCC UART parameter RAM */
	out_8(&uccup->common.rbmr, UCC_BMR_GBL \| UCC_BMR_BO_BE);		qe_iowrite8(UCC_BMR_GBL \| UCC_BMR_BO_BE, &uccup->common.rbmr);
	out_8(&uccup->common.tbmr, UCC_BMR_GBL \| UCC_BMR_BO_BE);		qe_iowrite8(UCC_BMR_GBL \| UCC_BMR_BO_BE, &uccup->common.tbmr);
	out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);		qe_iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
	out_be16(&uccup->maxidl, 0x10);		qe_iowrite16be(0x10, &uccup->maxidl);
	out_be16(&uccup->brkcr, 1);		qe_iowrite16be(1, &uccup->brkcr);
	out_be16(&uccup->parec, 0);		qe_iowrite16be(0, &uccup->parec);
	out_be16(&uccup->frmec, 0);		qe_iowrite16be(0, &uccup->frmec);
	out_be16(&uccup->nosec, 0);		qe_iowrite16be(0, &uccup->nosec);
	out_be16(&uccup->brkec, 0);		qe_iowrite16be(0, &uccup->brkec);
	out_be16(&uccup->uaddr[0], 0);		qe_iowrite16be(0, &uccup->uaddr[0]);
	out_be16(&uccup->uaddr[1], 0);		qe_iowrite16be(0, &uccup->uaddr[1]);
	out_be16(&uccup->toseq, 0);		qe_iowrite16be(0, &uccup->toseq);
	for (i = 0; i < 8; i++)		for (i = 0; i < 8; i++)
	out_be16(&uccup->cchars[i], 0xC000);		qe_iowrite16be(0xC000, &uccup->cchars[i]);
	out_be16(&uccup->rccm, 0xc0ff);		qe_iowrite16be(0xc0ff, &uccup->rccm);

	/* Configure the GUMR registers for UART */		/* Configure the GUMR registers for UART */
	if (soft_uart) {		if (soft_uart) {
	/* Soft-UART requires a 1X multiplier for TX */		/* Soft-UART requires a 1X multiplier for TX */
	clrsetbits_be32(&uccp->gumr_l,		qe_clrsetbits_be32(&uccp->gumr_l,
	UCC_SLOW_GUMR_L_MODE_MASK \| UCC_SLOW_GUMR_L_TDCR_MASK \|		UCC_SLOW_GUMR_L_MODE_MASK \| UCC_SLOW_GUMR_L_TDCR_MASK \| UCC_SLOW_GUMR_L_RDCR_MASK,
	UCC_SLOW_GUMR_L_RDCR_MASK,		UCC_SLOW_GUMR_L_MODE_UART \| UCC_SLOW_GUMR_L_TDCR_1 \| UCC_SLOW_GUMR_L_RDCR_16);
	UCC_SLOW_GUMR_L_MODE_UART \| UCC_SLOW_GUMR_L_TDCR_1 \|
	UCC_SLOW_GUMR_L_RDCR_16);

	clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,		qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
	UCC_SLOW_GUMR_H_TRX \| UCC_SLOW_GUMR_H_TTX);		UCC_SLOW_GUMR_H_TRX \| UCC_SLOW_GUMR_H_TTX);
	} else {		} else {
	clrsetbits_be32(&uccp->gumr_l,		qe_clrsetbits_be32(&uccp->gumr_l,
	UCC_SLOW_GUMR_L_MODE_MASK \| UCC_SLOW_GUMR_L_TDCR_MASK \|		UCC_SLOW_GUMR_L_MODE_MASK \| UCC_SLOW_GUMR_L_TDCR_MASK \| UCC_SLOW_GUMR_L_RDCR_MASK,
	UCC_SLOW_GUMR_L_RDCR_MASK,		UCC_SLOW_GUMR_L_MODE_UART \| UCC_SLOW_GUMR_L_TDCR_16 \| UCC_SLOW_GUMR_L_RDCR_16);
	UCC_SLOW_GUMR_L_MODE_UART \| UCC_SLOW_GUMR_L_TDCR_16 \|
	UCC_SLOW_GUMR_L_RDCR_16);

	clrsetbits_be32(&uccp->gumr_h,		qe_clrsetbits_be32(&uccp->gumr_h,
	UCC_SLOW_GUMR_H_TRX \| UCC_SLOW_GUMR_H_TTX,		UCC_SLOW_GUMR_H_TRX \| UCC_SLOW_GUMR_H_TTX,
	UCC_SLOW_GUMR_H_RFW);		UCC_SLOW_GUMR_H_RFW);
	}		}

	#ifdef LOOPBACK		#ifdef LOOPBACK
	clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,		qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
	UCC_SLOW_GUMR_L_DIAG_LOOP);		UCC_SLOW_GUMR_L_DIAG_LOOP);
	clrsetbits_be32(&uccp->gumr_h,		qe_clrsetbits_be32(&uccp->gumr_h,
	UCC_SLOW_GUMR_H_CTSP \| UCC_SLOW_GUMR_H_RSYN,		UCC_SLOW_GUMR_H_CTSP \| UCC_SLOW_GUMR_H_RSYN,
	UCC_SLOW_GUMR_H_CDS);		UCC_SLOW_GUMR_H_CDS);
	#endif		#endif

	/* Disable rx interrupts and clear all pending events. */		/* Disable rx interrupts and clear all pending events. */
	out_be16(&uccp->uccm, 0);		qe_iowrite16be(0, &uccp->uccm);
	out_be16(&uccp->ucce, 0xffff);		qe_iowrite16be(0xffff, &uccp->ucce);
	out_be16(&uccp->udsr, 0x7e7e);		qe_iowrite16be(0x7e7e, &uccp->udsr);

	/* Initialize UPSMR */		/* Initialize UPSMR */
	out_be16(&uccp->upsmr, 0);		qe_iowrite16be(0, &uccp->upsmr);

	if (soft_uart) {		if (soft_uart) {
	out_be16(&uccup->supsmr, 0x30);		qe_iowrite16be(0x30, &uccup->supsmr);
	out_be16(&uccup->res92, 0);		qe_iowrite16be(0, &uccup->res92);
	out_be32(&uccup->rx_state, 0);		qe_iowrite32be(0, &uccup->rx_state);
	out_be32(&uccup->rx_cnt, 0);		qe_iowrite32be(0, &uccup->rx_cnt);
	out_8(&uccup->rx_bitmark, 0);		qe_iowrite8(0, &uccup->rx_bitmark);
	out_8(&uccup->rx_length, 10);		qe_iowrite8(10, &uccup->rx_length);
	out_be32(&uccup->dump_ptr, 0x4000);		qe_iowrite32be(0x4000, &uccup->dump_ptr);
	out_8(&uccup->rx_temp_dlst_qe, 0);		qe_iowrite8(0, &uccup->rx_temp_dlst_qe);
	out_be32(&uccup->rx_frame_rem, 0);		qe_iowrite32be(0, &uccup->rx_frame_rem);
	out_8(&uccup->rx_frame_rem_size, 0);		qe_iowrite8(0, &uccup->rx_frame_rem_size);
	/* Soft-UART requires TX to be 1X */		/* Soft-UART requires TX to be 1X */
	out_8(&uccup->tx_mode,		qe_iowrite8(UCC_UART_TX_STATE_UART \| UCC_UART_TX_STATE_X1,
	UCC_UART_TX_STATE_UART \| UCC_UART_TX_STATE_X1);		&uccup->tx_mode);
	out_be16(&uccup->tx_state, 0);		qe_iowrite16be(0, &uccup->tx_state);
	out_8(&uccup->resD4, 0);		qe_iowrite8(0, &uccup->resD4);
	out_be16(&uccup->resD5, 0);		qe_iowrite16be(0, &uccup->resD5);

	/* Set UART mode.		/* Set UART mode.
	* Enable receive and transmit.		* Enable receive and transmit.
	@@ -743,22 +740,19 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
	* ...		* ...
	* 6.Receiver must use 16x over sampling		* 6.Receiver must use 16x over sampling
	*/		*/
	clrsetbits_be32(&uccp->gumr_l,		qe_clrsetbits_be32(&uccp->gumr_l,
	UCC_SLOW_GUMR_L_MODE_MASK \| UCC_SLOW_GUMR_L_TDCR_MASK \|		UCC_SLOW_GUMR_L_MODE_MASK \| UCC_SLOW_GUMR_L_TDCR_MASK \| UCC_SLOW_GUMR_L_RDCR_MASK,
	UCC_SLOW_GUMR_L_RDCR_MASK,		UCC_SLOW_GUMR_L_MODE_QMC \| UCC_SLOW_GUMR_L_TDCR_16 \| UCC_SLOW_GUMR_L_RDCR_16);
	UCC_SLOW_GUMR_L_MODE_QMC \| UCC_SLOW_GUMR_L_TDCR_16 \|
	UCC_SLOW_GUMR_L_RDCR_16);

	clrsetbits_be32(&uccp->gumr_h,		qe_clrsetbits_be32(&uccp->gumr_h,
	UCC_SLOW_GUMR_H_RFW \| UCC_SLOW_GUMR_H_RSYN,		UCC_SLOW_GUMR_H_RFW \| UCC_SLOW_GUMR_H_RSYN,
	UCC_SLOW_GUMR_H_SUART \| UCC_SLOW_GUMR_H_TRX \|		UCC_SLOW_GUMR_H_SUART \| UCC_SLOW_GUMR_H_TRX \| UCC_SLOW_GUMR_H_TTX \| UCC_SLOW_GUMR_H_TFL);
	UCC_SLOW_GUMR_H_TTX \| UCC_SLOW_GUMR_H_TFL);

	#ifdef LOOPBACK		#ifdef LOOPBACK
	clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,		qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
	UCC_SLOW_GUMR_L_DIAG_LOOP);		UCC_SLOW_GUMR_L_DIAG_LOOP);
	clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP \|		qe_clrbits_be32(&uccp->gumr_h,
	UCC_SLOW_GUMR_H_CDS);		UCC_SLOW_GUMR_H_CTSP \| UCC_SLOW_GUMR_H_CDS);
	#endif		#endif

	cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
	@@ -801,7 +795,7 @@ static int qe_uart_startup(struct uart_port *port)
	}		}

	/* Startup rx-int */		/* Startup rx-int */
	setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);		qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
	ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);		ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);

	return 0;		return 0;
	@@ -837,7 +831,7 @@ static void qe_uart_shutdown(struct uart_port *port)

	/* Stop uarts */		/* Stop uarts */
	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);		ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
	clrbits16(&uccp->uccm, UCC_UART_UCCE_TX \| UCC_UART_UCCE_RX);		qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX \| UCC_UART_UCCE_RX);

	/* Shut them really down and reinit buffer descriptors */		/* Shut them really down and reinit buffer descriptors */
	ucc_slow_graceful_stop_tx(qe_port->us_private);		ucc_slow_graceful_stop_tx(qe_port->us_private);
	@@ -857,9 +851,9 @@ static void qe_uart_set_termios(struct uart_port *port,
	struct ucc_slow __iomem *uccp = qe_port->uccp;		struct ucc_slow __iomem *uccp = qe_port->uccp;
	unsigned int baud;		unsigned int baud;
	unsigned long flags;		unsigned long flags;
	u16 upsmr = in_be16(&uccp->upsmr);		u16 upsmr = qe_ioread16be(&uccp->upsmr);
	struct ucc_uart_pram __iomem *uccup = qe_port->uccup;		struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
	u16 supsmr = in_be16(&uccup->supsmr);		u16 supsmr = qe_ioread16be(&uccup->supsmr);
	u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */		u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */

	/* Character length programmed into the mode register is the		/* Character length programmed into the mode register is the
	@@ -957,10 +951,10 @@ static void qe_uart_set_termios(struct uart_port *port,
	/* Update the per-port timeout. */		/* Update the per-port timeout. */
	uart_update_timeout(port, termios->c_cflag, baud);		uart_update_timeout(port, termios->c_cflag, baud);

	out_be16(&uccp->upsmr, upsmr);		qe_iowrite16be(upsmr, &uccp->upsmr);
	if (soft_uart) {		if (soft_uart) {
	out_be16(&uccup->supsmr, supsmr);		qe_iowrite16be(supsmr, &uccup->supsmr);
	out_8(&uccup->rx_length, char_length);		qe_iowrite8(char_length, &uccup->rx_length);

	/* Soft-UART requires a 1X multiplier for TX */		/* Soft-UART requires a 1X multiplier for TX */
	qe_setbrg(qe_port->us_info.rx_clock, baud, 16);		qe_setbrg(qe_port->us_info.rx_clock, baud, 16);