Commit 8b524514 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/pcie-rmw' 

- Add locking for read/modify/write PCIe Capability Register accessors for
  Link Control and Root Control (Ilpo Järvinen)

- Use PCIe RMW accessors for Link Control updates in PCI core, pciehp,
  amdgpu, radeon, mlx5, ath10k, ath11k, ath12k (Ilpo Järvinen)

- Convert PCIBIOS error values in mlx5 to generic errnos (Ilpo Järvinen)

- Simplify pcie_capability_clear_and_set_word() control flow (Bjorn
  Helgaas)

* pci/pcie-rmw:
  PCI: Simplify pcie_capability_clear_and_set_word() control flow
  net/mlx5: Convert PCI error values to generic errnos
  PCI: Document the Capability accessor RMW improvements
  wifi: ath10k: Use RMW accessors for changing LNKCTL
  wifi: ath12k: Use RMW accessors for changing LNKCTL
  wifi: ath11k: Use RMW accessors for changing LNKCTL
  net/mlx5: Use RMW accessors for changing LNKCTL
  drm/radeon: Use RMW accessors for changing LNKCTL
  drm/amdgpu: Use RMW accessors for changing LNKCTL
  PCI/ASPM: Use RMW accessors for changing LNKCTL
  PCI: pciehp: Use RMW accessors for changing LNKCTL
  PCI: Make link retraining use RMW accessors for changing LNKCTL
  PCI: Add locking to RMW PCI Express Capability Register accessors
parents d4a0f52c 294c1e4f

Documentation/PCI/pciebus-howto.rst

+9 −5
Original line number Diff line number Diff line
@@ -213,8 +213,12 @@ PCI Config Registers 
--------------------



Each service driver runs its PCI config operations on its own

capability structure except the PCI Express capability structure, in

which Root Control register and Device Control register are shared

between PME and AER. This patch assumes that all service drivers

will be well behaved and not overwrite other service driver's

configuration settings.
 
capability structure except the PCI Express capability structure,

that is shared between many drivers including the service drivers.

RMW Capability accessors (pcie_capability_clear_and_set_word(),

pcie_capability_set_word(), and pcie_capability_clear_word()) protect

a selected set of PCI Express Capability Registers (Link Control

Register and Root Control Register). Any change to those registers

should be performed using RMW accessors to avoid problems due to

concurrent updates. For the up-to-date list of protected registers,

see pcie_capability_clear_and_set_word().

drivers/gpu/drm/amd/amdgpu/cik.c

+10 −26
Original line number Diff line number Diff line
@@ -1574,17 +1574,8 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 
			u16 bridge_cfg2, gpu_cfg2;

			u32 max_lw, current_lw, tmp;



			pcie_capability_read_word(root, PCI_EXP_LNKCTL,

						  &bridge_cfg);

			pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,

						  &gpu_cfg);



			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;

			pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);



			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;

			pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,

						   tmp16);

			pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);

			pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);



			tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);

			max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
@@ -1637,21 +1628,14 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 
				msleep(100);



				/* linkctl */

				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);

				pcie_capability_write_word(root, PCI_EXP_LNKCTL,

							   tmp16);



				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);

				pcie_capability_write_word(adev->pdev,

							   PCI_EXP_LNKCTL,

							   tmp16);

				pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,

								   PCI_EXP_LNKCTL_HAWD,

								   bridge_cfg &

								   PCI_EXP_LNKCTL_HAWD);

				pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL,

								   PCI_EXP_LNKCTL_HAWD,

								   gpu_cfg &

								   PCI_EXP_LNKCTL_HAWD);



				/* linkctl2 */

				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

drivers/gpu/drm/amd/amdgpu/si.c

+10 −26
Original line number Diff line number Diff line
@@ -2276,17 +2276,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) 
			u16 bridge_cfg2, gpu_cfg2;

			u32 max_lw, current_lw, tmp;



			pcie_capability_read_word(root, PCI_EXP_LNKCTL,

						  &bridge_cfg);

			pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,

						  &gpu_cfg);



			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;

			pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);



			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;

			pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,

						   tmp16);

			pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);

			pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);



			tmp = RREG32_PCIE(PCIE_LC_STATUS1);

			max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@@ -2331,21 +2322,14 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) 


				mdelay(100);



				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);

				pcie_capability_write_word(root, PCI_EXP_LNKCTL,

							   tmp16);



				pcie_capability_read_word(adev->pdev,

							  PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);

				pcie_capability_write_word(adev->pdev,

							   PCI_EXP_LNKCTL,

							   tmp16);

				pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,

								   PCI_EXP_LNKCTL_HAWD,

								   bridge_cfg &

								   PCI_EXP_LNKCTL_HAWD);

				pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL,

								   PCI_EXP_LNKCTL_HAWD,

								   gpu_cfg &

								   PCI_EXP_LNKCTL_HAWD);



				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

							  &tmp16);

drivers/gpu/drm/radeon/cik.c

+10 −26
Original line number Diff line number Diff line
@@ -9534,17 +9534,8 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) 
			u16 bridge_cfg2, gpu_cfg2;

			u32 max_lw, current_lw, tmp;



			pcie_capability_read_word(root, PCI_EXP_LNKCTL,

						  &bridge_cfg);

			pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,

						  &gpu_cfg);



			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;

			pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);



			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;

			pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,

						   tmp16);

			pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);

			pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);



			tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);

			max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@@ -9591,21 +9582,14 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) 
				msleep(100);



				/* linkctl */

				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);

				pcie_capability_write_word(root, PCI_EXP_LNKCTL,

							   tmp16);



				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);

				pcie_capability_write_word(rdev->pdev,

							   PCI_EXP_LNKCTL,

							   tmp16);

				pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,

								   PCI_EXP_LNKCTL_HAWD,

								   bridge_cfg &

								   PCI_EXP_LNKCTL_HAWD);

				pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL,

								   PCI_EXP_LNKCTL_HAWD,

								   gpu_cfg &

								   PCI_EXP_LNKCTL_HAWD);



				/* linkctl2 */

				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

drivers/gpu/drm/radeon/si.c

+10 −27
Original line number Diff line number Diff line
@@ -7131,17 +7131,8 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 
			u16 bridge_cfg2, gpu_cfg2;

			u32 max_lw, current_lw, tmp;



			pcie_capability_read_word(root, PCI_EXP_LNKCTL,

						  &bridge_cfg);

			pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,

						  &gpu_cfg);



			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;

			pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);



			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;

			pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,

						   tmp16);

			pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);

			pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);



			tmp = RREG32_PCIE(PCIE_LC_STATUS1);

			max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@@ -7188,22 +7179,14 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 
				msleep(100);



				/* linkctl */

				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);

				pcie_capability_write_word(root,

							   PCI_EXP_LNKCTL,

							   tmp16);



				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);

				pcie_capability_write_word(rdev->pdev,

							   PCI_EXP_LNKCTL,

							   tmp16);

				pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,

								   PCI_EXP_LNKCTL_HAWD,

								   bridge_cfg &

								   PCI_EXP_LNKCTL_HAWD);

				pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL,

								   PCI_EXP_LNKCTL_HAWD,

								   gpu_cfg &

								   PCI_EXP_LNKCTL_HAWD);



				/* linkctl2 */

				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,