Commit 8cd7d9e1 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

dt-bindings: pinctrl: qcom,sdx55: fix matching pin config 



The TLMM pin controller follows generic pin-controller bindings, so
should have subnodes with '-state' and '-pins'.  Otherwise the subnodes
(level one and two) are not properly matched.

  qcom-sdx55-telit-fn980-tlb.dtb: pinctrl@f100000: 'pcie_ep_clkreq_default', 'pcie_ep_perst_default', 'pcie_ep_wake_default' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+'

This method also unifies the bindings with other Qualcomm TLMM and LPASS
pinctrl bindings.

Reviewed-by: default avatarBjorn Andersson <andersson@kernel.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221016170035.35014-29-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 7e300b5a

Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml

+11 −3
Original line number Diff line number Diff line
@@ -45,9 +45,17 @@ properties: 
  gpio-reserved-ranges:

    maxItems: 1



#PIN CONFIGURATION NODES

patternProperties:

  '-pins$':

  "-state$":

    oneOf:

      - $ref: "#/$defs/qcom-sdx55-tlmm-state"

      - patternProperties:

          "-pins$":

            $ref: "#/$defs/qcom-sdx55-tlmm-state"

        additionalProperties: false



$defs:

  qcom-sdx55-tlmm-state:

    type: object

    description:

      Pinctrl node's client devices use subnodes for desired pin configuration.
@@ -146,7 +154,7 @@ examples: 
                #interrupt-cells = <2>;

                interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;



                serial-pins {

                serial-state {

                        pins = "gpio8", "gpio9";

                        function = "blsp_uart3";

                        drive-strength = <8>;