Commit 8cf9575d authored by Mike Hsieh's avatar Mike Hsieh Committed by Alex Deucher
Browse files

drm/amd/display: Fix DSC enable sequence 



[Why]
DSC is enabled before reset link and potentially cause DSC enable fail problem.
[How]
Enable DSC after link is reseted

Signed-off-by: default avatarMike Hsieh <chun-wei.hsieh@amd.com>
Acked-by: default avatarBindu Ramamurthy <bindur12@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f9fc6f39

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+7 −3
Original line number Diff line number Diff line
@@ -3296,7 +3296,8 @@ void core_link_enable_stream( 


		/* eDP lit up by bios already, no need to enable again. */

		if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

					apply_edp_fast_boot_optimization) {

					apply_edp_fast_boot_optimization &&

					!pipe_ctx->stream->timing.flags.DSC) {

			pipe_ctx->stream->dpms_off = false;

#if defined(CONFIG_DRM_AMD_DC_HDCP)

			update_psp_stream_config(pipe_ctx, false);
@@ -3358,9 +3359,11 @@ void core_link_enable_stream( 
		/* Set DPS PPS SDP (AKA "info frames") */

		if (pipe_ctx->stream->timing.flags.DSC) {

			if (dc_is_dp_signal(pipe_ctx->stream->signal) ||

					dc_is_virtual_signal(pipe_ctx->stream->signal))

					dc_is_virtual_signal(pipe_ctx->stream->signal)) {

				dp_set_dsc_on_rx(pipe_ctx, true);

				dp_set_dsc_pps_sdp(pipe_ctx, true);

			}

		}



		if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

			dc_link_allocate_mst_payload(pipe_ctx);
@@ -3754,7 +3757,8 @@ bool dc_link_should_enable_fec(const struct dc_link *link) 
	if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&

			link->local_sink &&

			link->local_sink->edid_caps.panel_patch.disable_fec) ||

			link->connector_signal == SIGNAL_TYPE_EDP) // Disable FEC for eDP

			(link->connector_signal == SIGNAL_TYPE_EDP &&

					link->dc->debug.force_enable_edp_fec == false)) // Disable FEC for eDP

		is_fec_disable = true;



	if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

+2 −2
Original line number Diff line number Diff line
@@ -431,7 +431,7 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc, 
	DC_LOG_DSC("\tslice_width %d", config->slice_width);

}



static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)

bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable)

{

	struct dc *dc = pipe_ctx->stream->ctx->dc;

	struct dc_stream_state *stream = pipe_ctx->stream;
@@ -541,7 +541,7 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) 
		goto out;



	if (enable) {

		if (dp_set_dsc_on_rx(pipe_ctx, true)) {

		{

			dp_set_dsc_on_stream(pipe_ctx, true);

			result = true;

		}

drivers/gpu/drm/amd/display/dc/dc.h

+4 −0
Original line number Diff line number Diff line
@@ -541,6 +541,10 @@ struct dc_debug_options { 
	/* Enable dmub aux for legacy ddc */

	bool enable_dmub_aux_for_legacy_ddc;

	bool optimize_edp_link_rate; /* eDP ILR */

	/* force enable edp FEC */

	bool force_enable_edp_fec;

	/* FEC/PSR1 sequence enable delay in 100us */

	uint8_t fec_enable_delay_in100us;

};



struct dc_debug_data {

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

+2 −0
Original line number Diff line number Diff line
@@ -284,6 +284,8 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, 
	copy_settings_data->debug.u32All = 0;

	copy_settings_data->debug.bitfields.visual_confirm	= dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;

	copy_settings_data->debug.bitfields.use_hw_lock_mgr		= 1;

	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);

	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;



	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);

	dc_dmub_srv_cmd_execute(dc->dmub_srv);

drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h

+2 −0
Original line number Diff line number Diff line
@@ -88,5 +88,7 @@ bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable); 
bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);

void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);

bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);

bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);





#endif /* __DC_LINK_DP_H__ */